From Beginner to Expert in Embedded Hardware – Digital Circuits

Digital Circuit Fundamentals (Embedded Digital Circuits)

1. What are the phenomena of competition and hazard, and how to eliminate them

• Competition and Hazard Phenomena

1. Competition: In digital circuits, the phenomenon where multiple input signals change simultaneously, or the same signal reaches the input of the same logic gate via different paths, resulting in different arrival times of the signals.
2. Hazard: A temporary erroneous output level (e.g., a momentary low pulse when a high output is expected) at the output of a logic gate due to competition, which is a direct consequence of competition.
3. Hazard: The glitches caused by hazards may lead to erroneous operations in subsequent circuits (e.g., flip-flops flipping incorrectly, counters counting incorrectly).

• Methods of Elimination

1. Introduce Redundant Terms: By simplifying logical algebra, add redundant terms to the logical expression to eliminate hazards (e.g., AB + AC + BC, where BC is a redundant term that can eliminate hazards caused by simultaneous changes in A and B).
2. Add Enable Signals: Add gating logic at the output of the circuit, which only opens when the input signals are stable, ensuring correct output and avoiding glitches.
3. Connect Filter Capacitors: Connect small capacitors (e.g., 100pF to 1nF) in parallel at the output of logic gates to filter out high-frequency glitches (the capacitive reactance is small, allowing glitches to ground through the capacitor).
4. Optimize Circuit Structure: Reduce differences in signal transmission paths to ensure input signals change as synchronously as possible (e.g., shorten long paths, add buffers).
5. Use Synchronous Circuits: Convert asynchronous circuits to synchronous circuits, where all signal changes are controlled by clock pulses, avoiding free competition of input signals.

2. What are Synchronous Logic and Asynchronous Logic

• Synchronous Logic

1. Definition: In circuits, all flip-flops are controlled by a unified clock pulse, and changes in input signals only affect the output when the clock pulse is at its active edge (rising or falling).
2. Core Features:

• Has a unified clock, predictable circuit behavior, and simple timing analysis.
• Strong anti-interference capability, no competition hazards (or easily controlled).
• Higher power consumption (clock pulses continuously toggle, flip-flops frequently change states).
• Relatively complex circuit structure (requires clock distribution networks).

3. Applications: The vast majority of digital circuits (e.g., CPU, FPGA, microcontrollers, counters, shift registers).

• Asynchronous Logic

1. Definition: In circuits, there is no unified clock pulse, and the toggling of flip-flops is directly controlled by input signals or outputs from previous circuits, without the need for clock synchronization.
2. Core Features:

• No clock, low power consumption (only operates when signals change).
• Fast response speed (no need to wait for clock edges).
• Complex timing analysis, prone to competition hazards.
• Flexible circuit structure, suitable for low power and high-speed scenarios.

3. Applications: Simple logic circuits (e.g., asynchronous counters, level-triggered flip-flops), low-power IoT devices, high-speed interface circuits.

3. Concepts of Setup Time and Hold Time

Setup time (tsu) and hold time (th) are critical timing parameters for flip-flops (e.g., D flip-flops) that ensure the flip-flop can correctly sample input signals and stabilize outputs.

• Setup Time (tsu)

1. Definition: The minimum time that the input signal (e.g., the D signal of a D flip-flop) must remain stable before the active edge of the clock pulse (e.g., rising edge).
2. Significance: Ensures that the input signal is stable before the clock triggers, allowing the internal circuit of the flip-flop enough time to complete signal sampling.
3. Example: For a D flip-flop, tsu = 20ns means that the D signal must be stable for at least 20ns before the clock’s rising edge; otherwise, the flip-flop may sample incorrectly.

• Hold Time (th)

1. Definition: The minimum time that the input signal must continue to remain stable after the active edge of the clock pulse.
2. Significance: Ensures that the input signal does not change immediately after the clock trigger, avoiding interference with the sampling result of the flip-flop.
3. Example: For a D flip-flop, th = 10ns means that the D signal must remain stable for at least 10ns after the clock’s rising edge; otherwise, the output may become unstable.

• Key Considerations: Both setup time and hold time are inherent parameters of the flip-flop (determined by the device process). When designing circuits, it is essential to meet the requirements of “input signal setup time ≥ tsu, hold time ≥ th”; otherwise, timing violations may occur, leading to functional errors in the circuit.

4. Metastability and How to Resolve It

• Concept of Metastability

1. Definition: When the input signal of a flip-flop violates the setup time or hold time requirements, the output of the flip-flop is neither high nor low but in an unstable state (metastability), which may last for a period before randomly stabilizing to either high or low.
2. Hazard: Metastability can lead to incorrect outputs from the flip-flop, which may trigger a chain reaction of erroneous operations in subsequent circuits (e.g., incorrect counting in counters, abnormal transitions in state machines).
3. Common Scenarios: Asynchronous signals entering synchronous circuits (e.g., external button signals directly connected to the synchronous logic of an FPGA), cross-clock domain signal transmission (e.g., signals interacting between two clocks of different frequencies).

• Solutions

1. Two-stage Synchronizer (most common): Synchronize asynchronous signals through two cascaded flip-flops to the target clock domain. The first flip-flop may enter a metastable state, but the second flip-flop usually samples the first’s metastable state after the clock edge, resulting in a stable output signal.

• Applicable Scenarios: Single-bit asynchronous signal synchronization (e.g., buttons, interrupt signals).

2. Multi-stage Synchronizer: For high-frequency clocks or scenarios requiring higher reliability, use three or more cascaded flip-flops to further reduce the probability of metastability propagation.

3. Handshake Protocol: When transmitting multi-bit signals across clock domains, use handshake signals (e.g., valid, ack) to synchronize, ensuring the sender only sends signals when the receiver is ready, and the receiver samples the signal after it stabilizes.

4. Asynchronous FIFO: When transmitting large amounts of data across clock domains, use asynchronous FIFO as a buffer, with the FIFO’s read and write pointers synchronized using Gray code (where adjacent values change by only 1 bit) to avoid metastability.

5. Meet Timing Requirements: During the circuit design phase, ensure all signals meet setup time and hold time through timing analysis, reducing the occurrence of metastability from the source (suitable for synchronous circuits).

5. ROM, RAM, SRAM, DRAM, SDRAM

ROM (Read-Only Memory)

1. Characteristics: Data is not lost after power off (non-volatile), can only read data during normal operation, cannot write (or writing is difficult).
2. Types: Mask ROM (data written at the factory, cannot be modified), PROM (programmable once, cannot be modified after writing), EPROM (ultraviolet erasable, can be programmed multiple times), EEPROM (electrically erasable, can be modified at the byte level, e.g., 24C02), Flash ROM (flash memory, such as NAND Flash, NOR Flash, large capacity, electrically erasable, used for storing programs and data).
3. Applications: Storing microcontroller programs (NOR Flash), device firmware, fixed data (e.g., lookup tables).

RAM (Random Access Memory)

1. Characteristics: Data is lost after power off (volatile), can read and write data randomly, fast access speed.
2. Classification: SRAM and DRAM, primarily used for temporarily storing variables and data during program execution.

SRAM (Static RAM)

1. Storage Principle: Data is stored using flip-flops (bistable circuits made of MOS transistors) without needing refresh.
2. Characteristics: Fast access speed (ns level), low power consumption, high reliability; low integration, high cost, small capacity.
3. Applications: CPU cache (L1, L2 cache), internal RAM of FPGAs, high-speed data cache.

DRAM (Dynamic RAM)

1. Storage Principle: Data is represented by charge stored in capacitors, which leak and need to be refreshed periodically (every few ms) to maintain data.
2. Characteristics: High integration, large capacity, low cost; slower access speed than SRAM (μs level), requires refresh circuitry, higher power consumption.
3. Applications: Computer memory (e.g., DDR memory), large capacity data cache.

SDRAM (Synchronous DRAM)

1. Storage Principle: Based on DRAM, data read and write are synchronized with clock signals (synchronous DRAM), improving access speed.
2. Characteristics: Synchronized clock, high bandwidth, fast speed; requires refresh circuitry, large capacity, low cost.
3. Types: DDR SDRAM (Double Data Rate, e.g., DDR4, DDR5), which transmits data on both the rising and falling edges of the clock, increasing data transfer rates.
4. Applications: Main memory for computers, server memory, large capacity memory for embedded systems (e.g., set-top boxes, routers).

6. Differences Between IIR and FIR Filters

Comparison Item	IIR Filter (Infinite Impulse Response Filter)	FIR Filter (Finite Impulse Response Filter)
Impulse Response	Infinite (after input pulse, output signal continues to decay but does not disappear)	Finite (after input pulse, output signal returns to zero within a finite time)
Structural Characteristics	Contains feedback loops (output signal is fed back to the input)	No feedback loops (only feedforward structure)

Phase Characteristics	Non-linear phase (different frequency components of the signal have different phase shifts)	Can be designed for linear phase (all frequency components have phase shifts proportional to frequency), no phase distortion
Design Complexity	Complex (must consider stability to avoid oscillation)	Simple (no stability issues)
Computational Efficiency	High (lower order for the same filtering effect, less computation)	Low (higher order for the same filtering effect, more computation)

Stability	May be unstable (improper feedback coefficient design can cause oscillation)	Absolutely stable (no feedback, finite order)
Frequency Spectrum Characteristics	Steep amplitude-frequency characteristics (high filtering accuracy)	Relatively flat amplitude-frequency characteristics (requires high order to achieve steep characteristics)

Implementation Method	Can be implemented by digitizing analog filters (e.g., Butterworth, Chebyshev filters)	Designed directly using window function method, frequency sampling method
Application Scenarios	Scenarios where phase is not critical and high efficiency is pursued (e.g., audio amplification, communication signal filtering)	Scenarios sensitive to phase and requiring no distortion (e.g., speech recognition, image processing, data acquisition)