As AI large model training requires PB-level data throughput, smartphone imaging breaks through the 1-inch sensor size, and data center energy consumption requirements continue to decrease, traditional storage chips have long struggled to meet these “extreme demands”.
The continuous iteration of three core technologies: DDR5, HBM3, and 3D NAND is reconstructing the technological landscape of storage chips from the dimensions of “speed, bandwidth, and capacity”, becoming the “invisible cornerstone” driving computing power upgrades, terminal innovations, and efficient operation of data centers.
Today, we will break down the innovative highlights and practical scenarios of these three technologies to understand how storage chips are rewriting the future technology ecosystem.
Breakdown of the Three Technologies:
Individual Breakthroughs, Collaborative Empowerment
01DDR5: The “Speed Ceiling” of General Storage, the “Basic Engine” of Computing Power
As the successor to DDR4, DDR5 (fifth-generation double data rate memory) achieves a core breakthrough in “doubling the rate + improving energy efficiency”, becoming the “standard general storage” for PCs, servers, and gaming consoles.
Core Innovations:
Rate Surge: DDR5 starts at a rate of 3200MT/s, with a maximum exceeding 8400MT/s, which is 2.6 times that of DDR4 (maximum 3200MT/s), with data transfer latency as low as 16ns, allowing for rapid response to CPU’s high-frequency data calls;
Energy Efficiency Optimization: Utilizing a 1.1V low-voltage design, compared to DDR4’s 1.2V, power consumption is reduced by 15%-20% under the same load, while supporting On-Die ECC (on-chip error correction), significantly enhancing stability;
Capacity Expansion: The maximum capacity of a single memory module has reached 128GB, with server-side support for multi-channel parallelism, meeting the massive memory demands of AI training and big data analysis scenarios.
Typical Application Scenarios:
Consumer Side: High-end gaming PCs, flagship laptops, DDR5 increases game loading speed by 30%, and reduces stuttering rates for heavy tasks like video editing and 3D modeling by 50%;
Server Side: AI large model training servers, cloud computing data centers, DDR5 supports TB-level data exchange per second through high bandwidth, improving large model training efficiency by over 25%;
End Devices: Flagship smartphones, smart car cockpits, DDR5’s low power consumption + high speed meets the smooth experience of multitasking (e.g., navigation + audio + vehicle control systems running simultaneously).
02HBM3: The “Bandwidth King” of the AI Era, the “Dedicated Accelerator” of Computing Power
If DDR5 is the “generalist”, HBM3 (third-generation high bandwidth memory) is the “specialized champion” born for AI, addressing the pain point of traditional memory’s “insufficient bandwidth”.
Core Innovations:
Bandwidth Dominance: Utilizing 3D stacking technology, multiple DRAM chips are stacked vertically and connected via Through-Silicon Vias (TSV), achieving a single stack bandwidth of up to 1TB/s, which is 8-10 times that of DDR5, equivalent to transmitting 25 4K movies per second;
Density Upgrade: The maximum capacity of a single stack reaches 24GB, and after multi-stack packaging, the capacity can exceed 128GB, while the volume is only 1/10 of traditional memory, significantly saving motherboard space;
Leading Energy Efficiency: The power consumption per GB of bandwidth is only 1/3 that of DDR5, perfectly adapting to the high power consumption scenarios of AI chips, reducing overall energy consumption in data centers.
Typical Application Scenarios:
AI Chips: Large model training chips like ChatGPT (e.g., NVIDIA H100, AMD MI300) are equipped with HBM3, enabling rapid transmission of training data through high bandwidth, shortening large model training cycles from months to weeks;
High-end GPU/CPU: Professional graphics workstations, supercomputers, HBM3 connects directly to GPUs, solving the “data transfer bottleneck” in scenarios like 3D rendering and weather simulation;
Smart Driving: The domain controllers of autonomous vehicles need to process massive sensor data from cameras and radars in real-time, and HBM3’s high bandwidth and low latency ensure decision response speed.
033D NAND: The “Capacity Master” of Storage, the “Capacity Cornerstone” of End Devices
3D NAND (three-dimensional flash memory) replaces traditional 2D planar storage through “vertical stacking”, completely breaking through the physical limitations of capacity growth, becoming the core storage medium for solid-state drives (SSD) and mobile storage.
Core Innovations:
Stacking Layer Breakthrough:From the early 32 layers and 64 layers, it has now evolved to 512 layers and even 1024 layers. The more stacking layers, the larger the single chip capacity, with 512-layer 3D NAND achieving a single chip capacity of 1.6TB;
Performance and Cost Balance:Using TLC/QLC flash memory technology, while ensuring read and write speeds, significantly reduces the unit capacity cost, making 1TB SSD a mainstream choice in the consumer market;
Reliability Improvement:The new generation of 3D NAND supports higher P/E cycles (erase/write times), with some enterprise-grade products exceeding 100,000 times, while incorporating LDPC error correction algorithms for higher data security.
Typical Application Scenarios:
Consumer Electronics: Smartphones (1TB storage has become standard for flagship models), laptops/desktops (NVMe protocol 3D NAND SSDs, with read/write speeds reaching 7GB/s, boot time reduced to under 5 seconds);
Data Centers:Enterprise-grade SSD arrays, the high capacity + high IOPS (input/output operations per second) of 3D NAND support the massive data access needs of cloud computing and big data storage;
Embedded Devices:Smartwatches, security cameras, IoT sensors, small-sized 3D NAND chips provide high-capacity storage to meet local data caching needs of devices.
Technological Synergy:
Reconstructing the “Computing Power – Storage” Ecosystem
DDR5, HBM3, and 3D NAND do not exist in isolation but form a “synergistic and complementary” ecosystem:
AI Servers:HBM3 is responsible for high-bandwidth data exchange (supporting AI computing power) + DDR5 is responsible for general data caching (supporting system operation) + 3D NAND SSD is responsible for massive data storage (training data archiving), with the three working together to achieve “no bottleneck in computing power”;
Flagship Smartphones:DDR5 ensures multitasking smoothness + 3D NAND provides ultra-large storage space (to accommodate high-definition images and large applications), and some high-end models have begun exploring the application of HBM3 in mobile scenarios to further enhance AI computing speed;
Smart Cars:DDR5 supports the parallel operation of cockpit systems and driving assistance systems + HBM3 ensures real-time processing of sensor data + 3D NAND stores driving data and map information, constructing a “vehicle-grade storage ecosystem”.
Future Trends:
Faster, Larger, More Energy Efficient
DDR5 Continues to Speed Up: The next generation DDR5-10000 is about to go into mass production, with rates exceeding 10000MT/s, while DDR6 has entered the research and development stage, targeting rates of 16000MT/s to further support higher computing power demands;
HBM3 Evolves to HBM3e/HBM4: HBM3e bandwidth has exceeded 1.6TB/s, and HBM4 is expected to go into mass production in 2025, with bandwidth reaching over 2TB/s, while costs continue to decrease, likely penetrating from AI chips to high-end consumer electronics;
3D NAND Develops Towards “Higher Stacking + Faster Interfaces”: 1024-layer 3D NAND will become mainstream, while combined with PCIe 5.0/6.0 interfaces, SSD read/write speeds will exceed 10GB/s, and will explore intelligent caching technologies combined with AI to enhance data access efficiency.
In Conclusion
The technological evolution of storage chips has always been the “shadow of computing power upgrades”—as the demands of AI, big data, and smart terminals continue to break limits, the innovations of DDR5, HBM3, and 3D NAND have never ceased.
From PCs to servers, from smartphones to smart cars, these “invisible storage forces” are supporting every leap in technology. In the future, with further integration and cost optimization of these three technologies, not only will high-end technology products become more accessible, but they will also lay the storage foundation for next-generation scenarios such as the metaverse and quantum computing.
Recommended Positions
Salary Report
(For more salary reports, please follow the “Salary Research Institute” public account)
Contact Us:021-68403616