As the saying goes, to shoot a person, first shoot the horse; to capture a thief, first capture the king. The best way to solve EMC issues is to establish EMC rules for the PCBA. The following are my personal insights for reference!
1. Layer Configuration
1.1 Is the number of layers set reasonably?
1.1.1 Does the number of layers in the control board consider component density, inter-layer structure, the densest components, and the 5-5 principle?
1.1.2 The total number of power and ground layers should equal the number of signal layers.
1.1.3 Does the number of layers in the power board consider component density, smooth current flow, and power density?
1.2 Layer configuration and reference planes for power and ground
1.2.1 Does the layer configuration meet impedance control requirements while ensuring symmetrical lamination structure?
1.2.2 Are critical routing layers adjacent to the ground plane, preferably between two ground planes?
1.2.3 Do critical signals on adjacent layers not cross partition areas?
1.2.4 For single boards without reinforced insulation requirements, the spacing between power and ground layers should be ≤10 mil.
1.2.5 The power plane should be recessed at least 20H relative to the adjacent ground plane.
1.2.6 Remove unnecessary metal planes or set them as ground and connect them to the ground layer with vias.
1.2.7 Is the division of power and ground planes handled appropriately (division spacing ≥100 mil)?
1.2.8 Is the projection area of the routing layer within the projection area of the adjacent plane layers?
1.2.9 Is the gap length caused by vias, pads, etc., in the reference plane ≤500 mil?
1.2.10 For 6-layer single boards, are there no critical signal routings ≥50 MHz on the TOP and BOTTOM layers? If so, use the GUARD LINE method.
1.2.11 For single boards with a working frequency ≥50 MHz, if the second and second-to-last layers are routing layers, are the TOP and BOTTOM layers covered with ground copper foil?
1.2.12 Is the main working power plane adjacent to the corresponding ground plane?
1.2.13 Is the adjacent plane of the main component surface a ground plane?
2. Layout
2.1.1 Is there isolation between strong and weak currents, high and low voltages, high and low frequencies, input and output devices, and digital and analog signals?
2.1.2 Are filtering, protection, and isolation devices for interface signals placed as close as possible to the interface connectors, prioritizing protection before filtering?
2.1.3 Are power modules, filters, and power protection devices placed near the power entry to ensure the shortest input line for power, with separate routing for input and output without crossing?
2.1.4 Are sensitive devices and circuits placed away from radiation sources?
2.1.5 Are filtering capacitors for sensitive signals placed close to the receiving end?
2.1.6 Are crystals, oscillators, strong radiators, or sensitive devices at least ≥1000 mil from the edges of the board handles and port connectors?
2.1.7 Are oscillators and crystals arranged as centrally as possible on the PCB, with no routing beneath the oscillator, ensuring complete ground coverage, and no routing within 300 mil of the oscillator?
2.1.8 Are clock circuits, high-speed circuits, and memory circuits placed away from the outer edges of the printed circuit board?
2.1.9 Are low-frequency digital I/O circuits and analog I/O circuits arranged close to the connectors?
2.1.10 Are coupling capacitors placed close to the power pins of the oscillator, arranged in order of capacitance from large to small according to the direction of power flow?
2.1.11 For test points, avoid floating wires or keep them as short as possible, avoiding heat sinks, wires, etc.
2.1.12 Are filtering capacitors placed close to the power pins of the IC?
2.1.13 Is the routing of clock signals kept as short as possible, with wider traces, and is the circuit close to the load?
2.1.14 Is the overall layout based on the functional block diagram, with circuits of each functional module placed separately based on signal flow?
2.1.15 When placing multiple module circuits on the same PCB, are digital circuits separated from analog circuits, and high-speed circuits from low-speed circuits?
2.1.16 When placing multiple module circuits on the same PCB, are sensitive circuits separated from interference source circuits?
2.1.17 Is the position of Y capacitors prioritized for grounding hole placement?
2.1.18 When high-speed circuits are placed near the corresponding board edge connectors, are high, medium, and low-speed circuits arranged from near to far from the board edge connectors?
2.1.19 Except for optocouplers, ferrite beads, isolation transformers, A/D, D/A, etc., are other devices not crossing partition areas?
2.1.20 For filtering devices on the same differential pair, are they placed on the same layer, close, parallel, and symmetrically?
2.1.21 A segment of floating routing is allowed, avoiding the “antenna effect”.
2.1.22 In areas that can be directly hit by ESD, a ground line must be routed near every signal line.
3. Routing
3.1.1 Are routing corners greater than 90 degrees whenever possible, avoiding corners below 90 degrees, and not using 90-degree corners?
3.1.2 Power and corresponding ground lines should be as thick as possible, minimizing the loop area.
3.1.3 All signal lines should follow the minimum signal return path rule.
3.1.4 Are critical signal lines at least ≥3H (height from the reference plane) from the edge of the reference plane?
3.1.5 The spacing between shield ground lines and grounding holes should be ≤1000 mil.
3.1.6 Is the routing of filtering capacitors done first through the filtering capacitor and then to the device power pins?
3.1.7 Power and ground holes should have ≥2 thermal solder pad pins connected to the corresponding plane or copper foil.
3.1.8 Is the number of vias for critical signal lines such as clocks ≤3?
3.1.9 Are routing between digital and analog circuits, high and low-frequency circuits, and high and low-speed circuits not crossing or overlapping?
3.1.10 For components grounded to a metal shell, is ground copper foil laid on the top layer within their projection area, with solder mask windows opened in the corresponding area?
3.1.11 Does the length of critical signal lines meet the chip requirements?
3.1.12 X and Y capacitors need to be squeezed; if large currents are involved, solder mask windows should be opened.
3.1.13 The number of pins sharing a power and ground via should be ≤4.
3.1.14 The arrangement of wires should be as short as possible, especially in high-frequency circuits; all address lines or data lines of the same component should maintain similar lengths.
3.1.15 The length of signal lines should avoid being an integer multiple of one-fourth of the wavelength of the frequency of interest; otherwise, the signal line will resonate, causing strong radiated interference during resonance.
3.1.16 The width of the signal path from driver to load should be constant; variations in path width will change path impedance, causing discontinuities in line impedance, resulting in higher harmonics and reflections.
3.1.17 To avoid the “antenna effect,” pins controlled by integrated circuits should be grounded; generally, floating pins or routing should not be allowed.
3.1.18 Signal lines routed on multilayer PCBs should not form closed loops, as such loops will create loop antennas, generating strong electromagnetic radiation.
3.1.19 For strong interference circuits and sensitive circuits, such as clock lines, video lines, audio lines, reset lines, or other critical system routings, they should be forced to be routed on inner layers (preferably on selected routing layers), with shielding ground lines and using the 3W principle.
3.1.20 Differential line routing should be parallel, close, of equal length, and on the same layer; no other lines should be routed between the two lines of the differential pair.
3.1.21 Cross-slot routing is strictly prohibited; if cross-slot routing is necessary, ferrite beads should be added at the crossing point, and filtering should be applied to the routing at both ends of the slot.
3.1.22 Routing should not cross the slots of power planes; if design requires it, capacitors should connect different distinctions, and the capacitors should be placed at the signal path crossing the slot.
4. Double-Sided Boards
4.1.1 Do critical signal lines on double-sided boards have return ground lines, and is the loop area small?
4.1.2 On double-sided boards, are decoupling capacitors and shield ground lines connected to the ground of the device?
4.1.3 On double-sided boards, is the loop area between power and ground as small as possible?
4.1.4 On double-sided boards, if the power line and its return line exceed 7.5 cm, have high-frequency filtering capacitors been added every 7.5 cm between the two lines?