1. System Core Specifications and Requirements Analysis (Specification)
Sampling Rate: Maximum real-time sampling rate of 20 GSample/s.
For a single channel, the ADC sampling rate needs to reach 20GSPS.
For multi-channel interleaving, such as 4 channels, each channel ADC needs to reach 5GSPS.
Resolution: Typically between 8-bit and 12-bit. The resolution directly affects the data rate and system complexity. We will calculate using 8-bit as an example.
Data Rate:
Single channel data rate: 20G Sample/s * 8 bit/Sample = 160 Gbps.
This is the data rate processed internally by the FPGA, which is quite challenging.
Input Interface: Supports high-speed differential signal inputs, such as SLVS-EC, LVDS, etc.
Output Interface: Communicates with external systems (such as CPU, GPU) or storage units, typically high-speed serial interfaces, such as PCIe Gen3 x8 (≈8 GB/s) or PCIe Gen4 x8 (≈16 GB/s), or 10/100G Ethernet.
Trigger Function: Supports various trigger modes (edge, pulse width, window, etc.), with high trigger accuracy.
Storage Depth: Built-in large-capacity cache, such as DDR4 SDRAM, for temporary storage of high-speed data.
Core Functions: Real-time data acquisition, caching, triggering, preprocessing (such as denoising, filtering, data packaging), and transmission.
2. System Architecture Design
The entire system can be divided into the following core modules, as shown in the architecture diagram below:
text
+—————————–+
| Host (PC/Server) |
| |
+————-^—————+
| PCIe / Ethernet
+————-+—————+
| DMA & Interface |
| (PCIe/ETH MAC IP) |
+————-^—————+
| AXI4 Stream
+—————-+ +————–+—————-+
| Analog Input | | Data Processing Unit |
| & | | (Data Width Converter, FIFO) |
| High-Speed ADC| +————–^—————-+
+—————-+ |
| | AXI4 Stream
| 160 Gbps (8bit @20GSPS) |
+—-v—————————v—-+
| FPGA (Core Logic) |
| +——————————-+ |
| | Data Acquisition | |
| | (ISERDES, Clocking, Capture) | |
| +—————-^—————+ |
| | |
| +—————-v—————+ |
| | Trigger Logic | |
| | (Comparator, Pattern Match) | |
| +——————————-+ |
| | |
| +—————-v—————+ |
| | Memory Controller | |
| | (DDR4 Controller IP) | |
| +——————————-+ |
+————————————+
Data Flow: ADC -> FPGA Acquisition Module -> Trigger Logic -> DDR4 Cache -> Data Processing Unit -> DMA/Interface -> Host Computer.
3. Key Technology Module Design and Implementation
1. Front-End Data Acquisition and Synchronization (Data Acquisition & Synchronization)
This is the most critical module, responsible for receiving high-speed parallel data from the ADC.
Device Selection:
ADC: Choose an ADC that supports a sampling rate of 20GSPS (or achieves this through multiple interleaved chips), such as TI’s ADC12DJ3200 (12-bit, dual-channel 6.4GSPS or single-channel 12.8GSPS).
FPGA: Must select a high-end series, such as Xilinx UltraScale+ (e.g., KU series) or Intel Stratix 10. They must have sufficient high-speed IO (≥25Gbps), GTY/GTM transceiver resources, and logic units.
Interface Technology: The ADC and FPGA typically use the JESD204B/C high-speed serial interface.
JESD204B: Supports up to 12.5 Gbps/lane.
JESD204C: Supports up to 32 Gbps/lane.
To achieve 20GSPS 8-bit data, assuming using JESD204B (12.5Gbps):
Total Data Rate = 20G * 8 = 160 Gbps.
Required Number of Lanes = 160 Gbps / 12.5 Gbps/lane ≈ 13 Lanes. Typically rounded up and using more efficient encoding, may require 14 or 16 lanes.
Implementation: Use the JESD204B/C IP Core provided by the FPGA vendor. This IP is responsible for serialization/deserialization, alignment, decoding, and link synchronization, outputting parallel data to subsequent logic.
2. Clock Management and Synchronization (Clock Management)
Phase noise and jitter of the clock are key factors affecting the system’s signal-to-noise ratio (SNR).
Architecture: A super low-jitter clock generation and distribution network is required.
Clock Source: A super low phase noise reference clock (e.g., 100MHz OCXO) is provided to both the ADC and FPGA.
Inside FPGA: Use MMCM/PLL IP cores to generate various clocks required by the JESD204B IP and logic (Line Rate/40).
SYSREF: In JESD204B subclass 1, the SYSREF signal is required to achieve deterministic delay alignment for multi-link and multi-device. The timing relationship between SYSREF and the reference clock must be strictly guaranteed.
3. Trigger Logic (Trigger Logic)
Implementation: Implement a high-speed digital comparator inside the FPGA.
Compare the real-time data captured by the ADC with the trigger threshold set by the user through software.
Supports various modes: such as rising edge trigger (trigger when data exceeds the threshold), window trigger (trigger when data is within/outside high and low thresholds).
To precisely control the trigger position, pre-trigger and delayed trigger functions need to be designed, which are usually closely integrated with storage depth management.
4. Large Capacity Data Buffer (Data Buffer with DDR4)
Challenge: 160 Gbps of data cannot be transmitted to the host computer in real-time and must be buffered.
Solution: Use large-capacity, high-bandwidth DDR4 SDRAM external to the FPGA.
Calculated Bandwidth: The theoretical bandwidth of a DDR4-3200 is about 25.6 GB/s (≈205 Gbps). A write rate of 160 Gbps is already close to its limit.
Implementation: Use the DDR4 Memory Controller IP from the FPGA vendor.
Optimization:
Bit Width Expansion: Use a 72-bit or even wider interface to increase effective bandwidth.
Multi-Port Access: Design complex arbitration logic to balance access to memory between the acquisition side (writing) and the transmission side (reading).
Data Packaging: Package multiple samples into AXI bus widths (e.g., 512-bit) before writing to improve memory access efficiency.
5. Data Processing and Transmission (Data Processing & Transmission)
Data Width Conversion: Convert the data coming out of the JESD204B IP (possibly 128bit @500MHz) to a width suitable for writing to DDR4 (e.g., 512bit @125MHz).
DMA (Direct Memory Access): Design a DMA controller that can efficiently transfer blocks of data stored in DDR4 through high-speed interfaces when the host computer requests data, without excessive CPU intervention.
High-Speed Output Interfaces:
PCIe: Use PCIe Gen3 x8 (≈8 GB/s) or PCIe Gen4 x8 (≈16 GB/s) IP cores. This is the most commonly used solution, with low latency, suitable for block data transfer.
Ethernet: Use 100G Ethernet IP cores, more suitable for remote, streaming data transmission.
4. IP Core Design and Integration
Your goal is to design it as a reusable IP core.
Standard Interface: All internal modules communicate using AXI4-Stream interfaces for data communication and AXI4-Lite interfaces for control register configuration. This is the industry standard, facilitating integration and reuse.
Modular Design: Encapsulate each key technology module (acquisition, triggering, storage control, DMA) into independent, parameterized sub-IPs.
Top-Level Integration: Use Block Design/Qsys tools in Vivado/Quartus to connect these sub-IPs through AXI Interconnect to form a complete system.
Software Driver: Provide users with a simple software API for configuring sampling rates, trigger conditions, starting acquisition, reading data, etc.
5. Challenges and Countermeasures
Timing Closure: This is the biggest challenge. Any level of logic delay on the 160Gbps data path must be strictly controlled.
Strategy: Use a large number of pipeline registers; maintain high fan-out signals; use appropriate timing constraints; physically constrain critical paths.
Power Consumption and Heat Dissipation: Such high data rates mean significant power consumption.
Strategy: Choose appropriate FPGA models and packages; design good heat dissipation solutions (heat sinks, fans, or even liquid cooling); optimize logic in software, turning off unused modules.
Signal Integrity (SI/PI):
Strategy: PCB design is crucial. High-speed PCB materials (such as M6 grade or better) must be used, impedance must be strictly controlled, complete SI/PI simulations must be conducted, and power design must have ultra-low noise.
Cost: High-speed ADCs, high-end FPGAs, and high-speed PCB processes all mean high costs.
6. Conclusion
Designing a 20Gbps high-speed acquisition system IP is a top-tier hardware engineering project that requires designers to possess:
Deep FPGA development experience (especially in timing analysis and debugging).
Knowledge of high-speed digital circuits and signal integrity.
Understanding of high-speed protocols such as JESD204B/C, PCIe, DDR4, etc.
System-level architecture and integration capabilities.