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“ Modern FPGA design typically adopts a “top-down” approach. We design the I2C master controller starting from the top-level functionality and interfaces. So how do we begin from the top-level design, gradually decompose the functionality, define the interfaces, and ultimately implement an I2C controller that supports multi-byte read/write, error detection, and status monitoring? Follow this series of posts as we guide you through designing an I2C Master controller from scratch. In this post, we will delve into the functional planning and interface design of the IIC Master controller, mastering the complete design thinking from requirements to implementation.”
01 IIC Master Controller Interface Design
In modern FPGAs, the design phase generally employs a “top-down” design methodology. The core idea is to “define the top-level functionality and interfaces of the module system, and then gradually decompose it into smaller, more specific functional sub-modules until these sub-modules can be implemented using basic logic gates or IP cores.” Based on this, the IIC master controller starts with the design of its functionality and interfaces.
The functionality of the IIC master controller that this series aims to implement is as follows:
- Write operation: supports single byte and multi byte.
- Read operation: supports random read and continuous read.
- Error detection: supports arbitration loss, timing out, and bus occupation (busy).
- Status output: transmission in progress, transmission complete, transmission error.
Interface design of the IIC master controller Based on the above functionalities of the IIC master controller, the interface is designed as follows with 5 types:
- System input interface
- IIC bus interface
- IIC transmission control interface
- IIC status output interface
- IIC data interface
System input interface
The module has two system input signals, namely system clock and reset signal. The system input signal interface is as follows:
| Interface | Direction | Type | Bit | Description |
| clk_i | input | wire | 1 | System input clock. |
| rst_n | input | wire | 1 | System reset signal. |
IIC bus interface
The IIC bus consists of the SCL clock line and the SDA data line. The IIC bus interface is as follows:
| Interface | Direction | Type | Bit | Description |
| iic_scl | output | wire | 1 | IIC bus: synchronous clock line. |
| iic_sda | inout | wire | 1 | IIC bus: data line. |
IIC transmission control interface
For transmission control, the first step is to control the start of the transmission; secondly, it is necessary to implement random read and continuous read, requiring the selection of the read mode. The IIC transmission control interface design is as follows:
| Interface | Direction | Type | Bit | Description |
| iic_start | input | wire | 1 | Read/write data transmission enable signal: 1’b1 – enable.1’b0 – disable. |
| iic_read_mode | input | wire | 1 | Read mode control signal: 1’b1 – random read. 1’b0 – current read. |
IIC status output interface
A robust IIC master controller requires various status signals to be output. The IIC status output interface design is as follows:
| Interface | Direction | Type | Bit | Description |
| iic_busy | output | reg | 1 | Transmission busy signal: 1’b1 – busy. 1’b0 – idle. |
| iic_done | output | reg | 1 | Transmission complete signal. |
| iic_error | output | reg | 1 | Transmission error signal: 1’b1 – error. 1’b0 – normal. |
| error_code | output | reg | 3 | Error code: 3’d0 – normal. 3’d1 – no ACK response. 3’d2 – arbitration loss. 3’d3 – transmission timeout. 3’d4 – bus abnormal occupation. |
IIC data interface
To implement multi-byte read/write, it is necessary to clarify the byte length of the read transmission & write transmission. Therefore, the IIC data interface design is as follows:
| Interface | Direction | Type | Bit | Description |
| write_byte_len | input | wire | 8 | Write transmission: number of bytes N. |
| write_data | input | wire | N*8 | Write transmission: data. |
| read_byte_len | input | wire | 8 | Read transmission: number of bytes M. |
| read_data | output | reg | M*8 | Read transmission: data read. |
IIC master controller parameter design
For the functions in the table below, the design adopts parameters (instead of interfaces):
| Function | Description |
|
Variable length read/write |
Parameters: WMEN_LEN、RMEN_LEN Function: constrain the maximum number of bytes read and written. |
|
SCL clock generation |
Parameter: CLK_DIV Function: divide the system clock to generate a specific frequency SCL clock. |
|
Timeout detection |
Parameter: TIMEOUT_VAL Function: timeout duration for I2C bus transmission. |
IIC master controller interface Verilog code
The interface code for the iic_master_control module after the interface design is completed is as follows:
module iic_master_control #( parameter integer WMEN_LEN = 8 , // write data length. (bytes) parameter integer RMEN_LEN = 8 , // read data length. (bytes) parameter integer TIMEOUT_VAL = 100000000 , // over time count. (100M) parameter integer CLK_DIV = 499 // clk divider count.)( input wire clk_i , // system clock. input wire rst_n , // system reset signal. output wire iic_scl , // iic: clock. inout wire iic_sda , // iic: data. input wire [WMEN_LEN*8-1:0] write_data , // write data. input wire [7:0] write_byte_len , // write data byte len. output reg [RMEN_LEN*8-1:0] read_data , // read data. input wire [7:0] read_byte_len , // read data byte len. input wire iic_start , // transmit flag. input wire iic_read_mode , // transmit option. output reg iic_busy , // iic: busy. output reg iic_done , // iic: done. output reg iic_error , // iic: error. output reg [2:0] error_code // iic: error_code.);......endmodule02 Conclusion
Through this article, we have completed the functional definition and interface & parameter design of the IIC Master controller. From system input to IIC bus, from transmission control to status output, each interface carries the key responsibilities for the controller to work in collaboration with external systems. The next step will be to develop the state machine and data path design based on these interfaces, gradually achieving a fully functional and stable IIC Master controller. Stay tuned for future updates as we delve into the practical aspects of code implementation and simulation verification!
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