Chip Design | Basic Concepts (Part 8) Terminology Related to Tape-Out

Tape-out refers to the delivery of the final design data to the foundry for initial production, which is the most milestone-significant and also the most “costly” phase in the chip design process.

1. Decisions and Verification Before Tape-Out

1. MPW

• Full Name: Multi-Project Wafer

• Chinese: 多项目晶圆

• Explanation: A method to reduce tape-out costs. It involves placing multiple chip designs from different companies on the same wafer for manufacturing, thereby sharing the costs. This is the preferred solution for small companies, startups, and academic institutions to validate designs, in contrast to “full mask”.

2. Full Mask / Full Set Mask

• Chinese: 全光罩 / 全套光罩

• Explanation: A complete set of masks made for a single chip design. The cost is extremely high, but it offers the highest production efficiency and control, suitable for mass production. Typically, only large companies will adopt this for mature designs.

3. Shuttle

• Chinese: Shuttle 班车

• Explanation: The foundry regularly organizes MPW “shuttles”, which are fixed production cycles. Design companies need to ensure their designs “catch a ride” on a specific shuttle to proceed with MPW tape-out.

4. NTO

• Full Name: New Tape-Out

• Chinese: 新流片申请

• Explanation: The process of formally submitting a tape-out request to the foundry, including providing all necessary data files.

5. Sign-off

• Chinese: 签核

• Explanation: The final and most stringent verification phase before tape-out. All sign-off criteria must be met to proceed with tape-out, mainly including:

• Timing Sign-off: Ensures timing is met under all conditions.

• Physical Sign-off: Ensures DRC/LVS is completely clean.

• Power Sign-off: Confirms IR drop and electromigration are within controllable limits.

• DFM Sign-off: Design for manufacturability sign-off.

2. Tape-Out Data and Manufacturing Interface

1. GDSII

• Chinese: 版图数据流

• Explanation: The final file delivered for tape-out. This is a binary file that contains all geometric information of each layer of the chip’s mask. It is the final output of back-end design and serves as the direct basis for tape-out.

2. PDK

• Full Name: Process Design Kit

• Chinese: 工艺设计套件

• Explanation: A design data package provided by the foundry based on a specific process. It is the foundation of the entire chip design and includes:

• SPICE Model: Transistor-level simulation model.

• Technology File: Process technology document (used for DRC/LVS).

• Standard Cell Library: Standard cell library (timing, physical library).

• Design Rule: Design rules document.

3. DRM & DRC

• DRM: Design Rule Manual, a “legal document” established by the foundry that specifies all geometric size constraints.

• DRC: Design Rule Check, ensures GDSII complies with DRM requirements. DRC must be 100% clean to proceed with tape-out.

4. LVS

• Full Name: Layout vs. Schematic

• Chinese: 版图与原理图一致性检查

• Explanation: Ensures that the manufactured layout is electrically consistent with the designed schematic. LVS must pass.

3. Types and Strategies of Tape-Out

1. Risk Production / Engineering Sample

• Chinese: 风险生产 / 工程样品

• Explanation: The main purpose of the first tape-out is not for mass sales, but to produce a small number of samples for testing and validation, fixing any potential defects.

2. Production Tape-out

• Chinese: 量产流片

• Explanation: After the design passes comprehensive verification and is confirmed to be correct, tape-out is conducted for large-scale market sales. The GDSII used for this tape-out is the final confirmed “golden version”.

3. Re-spin / Re-tapeout

• Chinese: 重新流片

• Explanation: If issues are found during testing of the chips from the first tape-out, the design needs to be modified and re-taped. This is a very costly and time-consuming failure.

• Metal Spin: If the error can be fixed by modifying only the metal layer without touching the underlying transistors, costs and time will be significantly reduced.

4. Post-Tape-Out and Chip Validation

1. First Silicon / First Chip

• Chinese: 首颗芯片

• Explanation: Refers to the first batch of physical chip samples produced from the first tape-out.

2. Bring-up / Characterization

• Chinese: 芯片启动 / 特性测试

• Explanation: Powering up the first chip on a dedicated test board and conducting comprehensive functional and performance tests to verify compliance with design specifications.

3. Bench Testing / Lab Validation

• Chinese: 板级测试 / 实验室验证

• Explanation: Testing the chip in real or simulated application environments, such as installing it on a mobile phone motherboard to test compatibility and overall performance with other components.

4. Yield / Yield Rate

• Chinese: 良率 / 良率

• Explanation: Refers to the percentage of functional chips on a wafer. The yield rate for the first tape-out is usually low, improving as process maturity increases. Yield directly determines the cost and profit of the chips.

5. Failure Analysis

• Chinese: 失效分析

• Explanation: If chip testing fails, various precision instruments (such as electron microscopes) are used to “dissect” the chip, locating and analyzing the root cause of the failure to provide a basis for re-spin.

5. Other Important Terms

1. ECO

• Full Name: Engineering Change Order

• Chinese: 工程变更指令

• Explanation: Last-minute modifications to the design before or even after tape-out. If it can be achieved by modifying only the metal layer, it can save a lot of costs and time.

2. ESD / Latch-up

• Chinese: 静电放电 / 闩锁效应

• Explanation: Two major reliability threats that the chip must withstand during manufacturing, packaging, testing, and usage. Strict ESD and latch-up simulations and rule checks must be passed before tape-out.