Assembly Language Explained: Page Translation from Linear Address to Physical Address

Basic Concepts of Page Translation

In protected mode, if paging is enabled, the processor needs to convert a 32-bit linear address to a 32-bit physical address. This process involves three key data structures:

; Relevant control registers
CR0 ; Contains the paging enable bit PG
CR3 ; Page Directory Base Register (PDBR)

Data Structures for Page Translation

Page Directory Entry Structure

; Page Directory Entry Format
; Bits 31-12: Page Table Base Address
; Bits 11-9: Available Bits
; Bit 8: G (Global Page)
; Bit 7: PS (Page Size, 0=4KB)
; Bit 6: D (Dirty Bit)
; Bit 5: A (Access Bit)
; Bit 4: PCD (Cache Disable)
; Bit 3: PWT (Write Through)
; Bit 2: U/S (User/Supervisor)
; Bit 1: R/W (Read/Write)
; Bit 0: P (Present Bit)

Page Table Entry Structure

; Page Table Entry Format
; Bits 31-12: Page Frame Base Address
; Bits 11-9: Available Bits
; Bit 8: G (Global Page)
; Bit 7: PAT (Page Attribute Table)
; Bit 6: D (Dirty Bit)
; Bit 5: A (Access Bit)
; Bit 4: PCD (Cache Disable)
; Bit 3: PWT (Write Through)
; Bit 2: U/S (User/Supervisor)
; Bit 1: R/W (Read/Write)
; Bit 0: P (Present Bit)

Address Translation Process

Decomposing the Linear Address

; Decomposing a 32-bit linear address (4KB page):
; Bits 31-22: Page Directory Index (10 bits)
; Bits 21-12: Page Table Index (10 bits)
; Bits 11-0:  Page Offset (12 bits)

Detailed Steps of the Translation

; Assume the linear address to be converted is in EAX
mov eax, [linear_address]  ; Load the linear address

; Step 1: Extract the Page Directory Index
mov ebx, eax
shr ebx, 22                ; Shift right 22 bits to get the Page Directory Index
and ebx, 0x3FF             ; Ensure it is in the range 0-1023

; Step 2: Get the Page Directory Entry
mov edi, cr3               ; Get the physical base address of the page directory
and edi, 0xFFFFF000        ; Clear the lower 12 bits
mov esi, [edi + ebx*4]     ; Read the Page Directory Entry

; Check the Present Bit of the Page Directory Entry
test esi, 1
jz page_fault_handler      ; If not present, jump to page fault handler

; Step 3: Extract the Page Table Index
mov ebx, eax
shr ebx, 12                ; Shift right 12 bits
and ebx, 0x3FF             ; Get the Page Table Index

; Step 4: Get the Page Table Entry
mov edi, esi
and edi, 0xFFFFF000        ; Get the Page Table Base Address
mov esi, [edi + ebx*4]     ; Read the Page Table Entry

; Check the Present Bit of the Page Table Entry
test esi, 1
jz page_fault_handler      ; If not present, jump to page fault handler

; Step 5: Combine to form the Physical Address
mov edi, esi
and edi, 0xFFFFF000        ; Get the Page Frame Base Address
mov ebx, eax
and ebx, 0xFFF             ; Get the Page Offset
or edi, ebx                ; Combine to get the Physical Address

; At this point, EDI contains the Physical Address

Example of Page Table Setup

section .data
align 4096
page_directory:
    times 1024 dd 0        ; Page Directory: 1024 double words

page_table:
    times 1024 dd 0        ; Page Table: 1024 double words

section .text
global enable_paging

enable_paging:
    ; Initialize the Page Table
    mov edi, page_table
    mov eax, 0x00000000    ; Physical address starts from 0
    mov ecx, 1024          ; 1024 Page Table Entries

.init_page_table:
    or eax, 0x003          ; Set Present and Read/Write bits
    mov [edi], eax
    add eax, 4096          ; Next 4KB page
    add edi, 4
    loop .init_page_table

    ; Set up the Page Directory
    mov edi, page_directory
    mov eax, page_table
    or eax, 0x003          ; Present + Read/Write bits
    mov [edi], eax         ; First Page Directory Entry points to the Page Table

    ; Set the CR3 Register
    mov eax, page_directory
    mov cr3, eax

    ; Enable Paging
    mov eax, cr0
    or eax, 0x80000000     ; Set PG bit
    mov cr0, eax

    ret

Page Fault Handling

page_fault_handler:
    pushad                 ; Save all general-purpose registers

    mov eax, cr2           ; CR2 contains the linear address that caused the page fault

    ; Check the type of error
    push eax
    call handle_page_fault ; Call high-level page fault handler
    add esp, 4

    popad                  ; Restore registers
    iret                   ; Return from interrupt

4MB Large Page Configuration

; For 4MB large pages, the decomposition of the linear address is different:
; Bits 31-22: Page Directory Index (10 bits)
; Bits 21-0:  Page Offset (22 bits)

setup_4mb_pages:
    mov edi, page_directory
    mov eax, 0x00000000
    mov ecx, 1024

.init_4mb_pages:
    or eax, 0x083          ; Set PS bit (large page) + Present + Read/Write bits
    mov [edi], eax
    add eax, 0x400000      ; Next 4MB page
    add edi, 4
    loop .init_4mb_pages

    ret

Performance Optimization Techniques

; Using TLB Invalidation Instructions
invalidate_tlb:
    mov eax, cr3
    mov cr3, eax           ; Reload CR3 to flush TLB

; Or use specific address to flush
invalidate_tlb_entry:
    invlpg [eax]           ; Invalidate TLB entry for specific linear address

Conclusion

The page translation mechanism is a core feature of modern processor memory management:

1. Three-Level Structure: Page Directory → Page Table → Physical Page Frame
2. Address Decomposition: 10-bit Directory Index + 10-bit Page Table Index + 12-bit Offset
3. Control Registers: CR3 stores the physical address of the Page Directory
4. Flexibility: Supports 4KB and 4MB pages, multi-task isolation

This mechanism provides powerful memory protection and virtual memory capabilities for operating systems, forming the foundation of modern computing systems.