Chapter 1 Basic Knowledge
1.1 Machine Language
Machine language is a collection of machine instructions. Machine instructions are commands that a machine can execute correctly.
1.2 The Emergence of Assembly Language
The main body of assembly language consists of assembly instructions. The difference between assembly instructions and machine instructions lies in their representation. Assembly instructions are a mnemonic form of machine instructions. Registers: Simply put, they are devices in the CPU that can store data, and there are multiple registers in a CPU. The computer can only understand machine instructions, so how can we make the computer execute programs written by programmers using assembly instructions?
1.3 Components of Assembly Language
1. Assembly instructions (mnemonics for machine instructions) 2. Pseudo-instructions (executed by the compiler) 3. Other symbols (recognized by the compiler) The core of assembly language is assembly instructions, which determine the characteristics of the assembly language.
1.4 Memory
The CPU is the core component of the computer, controlling its operation and performing calculations. To make a CPU work, the BIU must provide it with instructions and data. Instructions and data are stored in memory, which is commonly referred to as RAM.
1.5 Instructions and Data
Instructions and data are application concepts. In memory and on disk, there is no distinction between instructions and data; both are binary information.
1.6 Memory Units
Memory is divided into several storage units, each sequentially numbered starting from 0. For large capacity memory, the following units are commonly used: 1B = 8BIT 1KB = 1024B 1M = 1024KB 1G = 1024M
1.7 CPU Read/Write to Memory
For the CPU to read/write data, it must interact with external devices through three types of information: Address Information (AS) Control Information (CS) Data Information (DS) So how does the CPU transmit address, data, and control information to memory? In a computer, there are special wires that connect the CPU and other devices, commonly referred to as buses. Address Bus (AB) Data Bus (DB) Control Bus (CB)
1.8 Address Bus
The CPU specifies memory units through the address bus. The number of different pieces of information that can be transmitted on the address bus determines how many memory units the CPU can address. How does the address bus emit address information? If a CPU has N address lines, we can say that the width of the address bus is N, allowing the CPU to address up to 2 to the power of N memory units.
1.9 Data Bus
Data transfer between the CPU and memory or other devices is conducted via the data bus. The width of the data bus determines the speed of data transmission between the CPU and the outside world.
1.10 Control Bus
The CPU controls external devices through the control bus. Here, the control bus is a collective term, comprising several different control lines. The number of control lines means the number of control types the CPU can provide to external devices.
1.12 Motherboard
Every PC has a motherboard, which contains core components and some main devices. These devices are connected through buses (address bus, data bus, control bus).
1.13 Interface Cards
In a computer system, all usable programs must be controlled by the CPU. The CPU cannot directly control external devices like monitors, speakers, and printers. The devices are directly controlled by interface cards plugged into expansion slots, such as graphics cards, network cards, and sound cards.
1.14 Various Memory Chips
They are divided into two types based on read/write properties: Random Access Memory (RAM) and Read-Only Memory (ROM). ROM contains BIOS. BIOS: BASIC INPUT/OUTPUT SYSTEM is a basic input/output system provided by motherboard and various interface card manufacturers. It can be used to perform basic input/output operations through the software. The corresponding ROM is plugged into the motherboard and some interface cards.
1.15 Memory Address Space
1. All are related to the CPU's bus vector. 2. When the CPU reads/writes them, it issues memory read/write commands through the control bus. Memory address space: all physical memory is viewed as a logical memory consisting of several storage units, each physical memory occupying an address segment, i.e., a segment of address space. The CPU reads/writes data in this address space, which is actually reading/writing data in the corresponding physical memory. The allocation of memory address space in the system is known, with starting and ending addresses: 0000 - 7FFF main memory storage space (RAM) 8000 - 9FFF video memory address A000 - FFFF various ROM. Ultimately, the CPU runs the program. When programming in assembly, we must consider the problem from the CPU's perspective. For the CPU, all storage units in the system are in a unified logical memory, and its capacity is limited by the CPU's addressing ability. This logical memory is what we refer to as the memory address space.
Chapter 2 Registers (CPU Working Principle)
A typical CPU consists of an arithmetic unit, a controller, registers, and other components, which are connected by an internal bus. The 8086 CPU has 14 registers: AX, BX, CX, DX, SI, DI, SP, BP, IP, CS, SS, DS, ES, PSW.
2.1 General Registers
The registers in the previous generation of CPUs are all 8-bit. To ensure compatibility, these four registers can be divided into two independent 8-bit registers: AX AH AL, BX BH BL, CX CH CL, DX DH DL.
2.2 Word Storage in Memory
A word can be stored in a 16-bit register, with the high byte and low byte of this word naturally placed in the high and low 8-bit registers of this register.
2.3 Several Assembly Instructions
Assembly instructions are case-insensitive. MOV AX, 18 AX = 18 MOV AH, 78 AH = 78 ADD AX, 8 AX = 8 MOV AX, BX AX = BX ADD AX, BX AX = AX + BX.
2.4 Physical Address
The CPU needs to provide the address of the memory unit to access it. The storage space composed of all memory units is a one-dimensional linear space. We call this unique address the physical address.
2.5 16-Bit Structure CPU
In summary, the 16-bit structure describes the following features of a CPU: 1. The arithmetic unit can process up to 16 bits of data at a time. 2. The maximum width of the registers is 16 bits. 3. The path between the registers and the arithmetic unit is 16 bits.
2.6 How the 8086 CPU Provides Physical Address
The 8086 has a 20-bit address bus, capable of transmitting 20-bit addresses, with an addressing capacity of 1M. The internal structure of the 8086 is 16 bits, meaning it can only transmit 16-bit addresses, resulting in an effective addressing capacity of only 64k. The 8086 CPU uses a method of combining two 16-bit addresses internally to form a 20-bit address: Physical Address = Segment Address x 16 + Offset Address. The more commonly used term for "Segment Address x 16" is left-shifting the data by 4 bits (binary).
2.8 Concept of Segment
Memory is not segmented; the segmentation is determined by the CPU. Since the 8086 CPU provides the physical address of memory units using the formula "Physical Address = Segment Address x 16 + Offset Address", it allows us to manage memory in a segmented manner. In programming, we can group several consecutive memory units into a segment as needed, using the segment address x 16 to locate the starting address (base address) of the segment and the offset address to locate memory units within the segment. Two points to note: 1. The segment address x 16 must be a multiple of 16, so the starting address of a segment is also a multiple of 16. 2. The offset address is 16 bits, and the addressing capacity of a 16-bit address is 64k, so the maximum length of a segment is 64k.
2.9 Segment Registers
Segment registers provide segment addresses. The 8086 CPU has four segment registers: CS, DS, ES, SS. When the 8086 CPU needs to access memory, it relies on these four segment registers to provide the segment address of the memory unit. CS and IP are the most critical registers in the 8086 CPU, indicating the address of the instruction the CPU is currently reading. CS is the code segment register, IP is the instruction pointer register. 1. Read instructions from memory units pointed to by CS:IP, buffering them. 2. IP = IP + length of the read instruction, pointing to the next instruction. 3. Execute the instruction, returning to step 1 and repeating the process.
2.10 CS and IP
At any time, the CPU uses the contents of CS and IP as the segment address and offset address of the instruction, combining them to form the physical address of the instruction in memory for execution. If a segment of information in memory has been executed by the CPU, then its corresponding memory unit must have been pointed to by CS:IP. How can we change the values of CS and IP?
2.11 Instructions to Modify CS and IP
JMP Segment Address: Offset Address.
2.12 Code Segment
For the 8086, during programming, we can define a group of memory units as a segment based on our needs. We can define a memory unit of length N (N ≤ 64KB), a continuous group of addresses, with the starting address being a multiple of 16, to store code, thus defining a code segment. How do we execute the instructions in the code segment? Simply defining a memory unit as a code segment does not mean that the CPU will automatically treat the instructions in the defined code segment as executable instructions. Therefore, we must point the CS:IP to the address of the first instruction in the code segment.
Chapter 3 Registers
3.1 Storage of Words in Memory
Any two consecutive memory units, unit N and unit N+1, can be viewed as two memory units, or as the high byte unit and low byte unit in the memory unit with address N.
3.2 DS and [address]
When the CPU needs to read a memory unit, it must first provide the address of that memory unit. In the 8086 PC, memory addresses consist of segment addresses and offset addresses. The DS register in the 8086 CPU is usually used to store the segment address of the data to be accessed. The MOV instruction's functions are: 1. Directly send data to a register. 2. Send the contents of one register to another register. 3. Transfer the contents of a memory unit to a register. The 8086 CPU does not support directly sending data to segment registers. Data --> General Register --> Segment Register.
3.3 Transfer of Words
Since the 8086 CPU has 16-bit registers and 16 data lines, it can transfer 16 bits of data at once, which is equivalent to transferring a word at once.
3.4 MOV ADD SUB Instructions
MOV Register, Data MOV Register, Register MOV Register, Memory Unit MOV Memory Unit, Register MOV Segment Register, Register ADD and SUB instructions are similar to MOV, both having two operands.
3.5 Data Segment
For the 8086 PC, we can define a group of memory units as a segment (which can be a code segment or data segment) according to our needs. We can define a segment of memory units of length N (N ≤ 64k), continuous addresses, with a starting address that is a multiple of 16, as a memory space specifically for storing data, thus defining a data segment. How do we access data in the data segment? Treating a segment of memory as a data segment is just an arrangement during programming; when performing specific operations, we can use DS to store the segment address of the data segment, and when necessary, access specific units in the data segment using related instructions. To access a memory unit with the MOV instruction, we can specify only the offset address of the memory unit in the MOV instruction, while the segment address defaults to the DS register.
3.6 Stack
A stack is a type of storage space with a special access method. Its uniqueness lies in that the last data entered into this space is the first to be removed. The stack has two basic operations: push and pop. Push: Place a new element on the top of the stack. Pop: Remove an element from the top of the stack. The top element of the stack is always the last one pushed, and when it needs to be popped, it is the first to be removed from the stack.
3.7 Stack Mechanism Provided by the CPU
Modern CPUs have stack designs. The 8086 CPU provides relevant instructions to access memory spaces in a stack manner. This means that when programming based on the 8086 CPU, we can use a segment of memory as a stack. The 8086 CPU provides push and pop instructions. The push and pop operations of the 8086 CPU are performed word by word. 1. How does the CPU know a segment of memory is used as a stack? 2. When executing push and pop, how does it know which unit is the top of the stack? In the 8086 CPU, there are two registers: segment register SS stores the segment address of the top of the stack, and register SP stores the offset address of the top of the stack. PUSH AX; (SP) <-- (SP) - 2 Sends the contents of AX to the memory unit pointed to by SS:SP, with SS:SP currently pointing to the top of the stack. POP AX; Sends the memory unit pointed to by SS:SP into AX. (SP) <-- (SP) + 2 SS:SP currently points to the top of the stack. At any time, SS:SP points to the top element of the stack. When the stack is empty, there are no elements in the stack, and thus no top element exists, so SS:SP can only point to the unit below the bottom element of the stack. The offset address of this unit is the offset address of the bottom word unit of the stack + 2.
3.8 Stack Overflow Issue
SS and SP only record the address of the top of the stack, and it is based on SS and SP that we can ensure that we find the top of the stack during push and pop operations. However, how can we ensure that the top of the stack does not exceed the stack space during push and pop? Using the PUSH instruction to push data when the stack is full, or using POP to pop data when the stack is empty, will inevitably lead to stack overflow issues. We might wonder, since we have designated a space as a stack, it is very likely that there are other data, code, etc., with different purposes stored in the space outside the stack. This data and code may come from our own program or from other programs. For example, in the CPU, there are registers that record the upper and lower limits of the stack. We could specify the range of the stack space by filling in these registers, and then the CPU could detect the upper limit register when executing the push instruction and the lower limit register when executing the pop instruction to ensure that overflow does not occur. In practice, the 8086 CPU does not provide such registers. The current top of the stack, which instruction is being executed.
3.9 PUSH.POP Instructions
The stack space is, of course, also a part of memory space; it is just a segment of memory space that can be accessed in a special way. PUSH and POP are essentially memory transfer instructions that can transfer data between registers and memory units. Unlike MOV instructions, the addresses of the memory units accessed by PUSH and POP instructions are not given in the instruction but are pointed to by SS:SP. At the same time, the PUSH and POP instructions also change the contents of SP. PUSH and POP and other stack operation instructions only modify SP. This means that the maximum change range of the top of the stack is: 0000 - FFFFH. The 8086 CPU only records the top of the stack, and we must manage the size of the stack space ourselves.
3.10 Stack Segment
For the 8086 PC, we can define a segment of memory units as a stack as needed. We can define a segment of length N (N ≤ 64k), continuous addresses, with a starting address that is a multiple of 16, as a memory space specifically for storing data, thus defining a stack segment. The change range of the top of the stack is 0000 - FFFFH, from SP = 0 when the stack is empty, pushing until the stack is full at SP = 0. If we push again, the top of the stack will wrap around, overwriting the contents of the original stack. A memory segment can be a storage space for code, data, or a stack, or it can be nothing at all. The key lies in the settings of the registers in the CPU.
Chapter 4 The First Program
4.1 The Process of Writing and Executing a Source Program
Writing: Use a text editor (notepad++ UltraEdit) to write the source program in assembly language. Compiling: Use an assembly language compiler (MASM.EXE) to compile the source program in the source file, producing an object file. Linking: Use a linking program (LINK.EXE) to link the object file, generating an executable file that can be run directly in the operating system. The executable file contains two parts: the program (machine code translated from assembly instructions in the source program) and data (data defined in the source program) along with relevant descriptive information (how large the program is, how much memory it occupies).
4.2 Source Program
Assembly instructions: instructions with corresponding machine codes that will ultimately be executed by the CPU. Pseudo-instructions: instructions without corresponding machine codes that are not executed by the CPU but are executed by the compiler. Defining a segment: segment and ends are a pair of pseudo-instructions used together, which must be used when writing a compilable assembly program. The segment and ends define a segment, with segment indicating the start of a segment and ends indicating the end of a segment. A segment must have a name to represent it, formatted as: SegmentName segment SegmentName ends. An assembly program consists of multiple segments used to store code, data, or as stack space. A meaningful assembly program must have at least one segment to store code. END is a marker for the end of an assembly program. If the program is completed, the pseudo-instruction END should be added at the end; otherwise, the compiler will not know where the program ends during compilation. ASSUME associates a register with a segment. It assumes that a certain segment register is related to a segment defined in the program using segment...ends. By using assume, this association can be specified, allowing the compiler to associate the segment register with a specific segment when needed. Labels: A label refers to an address.
4.3 Editing the Source Program
4.4 Compiling
4.5 Linking
When the source program is large, it can be divided into multiple source files for compilation. After each source program is compiled into an object file, a linking program is used to link them together, generating an executable file. If the program calls subroutines from a library file, that library file must be linked with the object files generated from this program to create an executable file.
4.6 Simplified Compilation and Linking
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4.7 Executing EXE
4.8 The Principle of Loading and Running Programs in Executable Files
The shell of the operating system The operating system is a large, complex software system composed of multiple functional modules. Any general-purpose operating system must provide a program called a shell for users to operate the computer. In DOS, there is a program called command.com, which is referred to as the command interpreter in DOS, or the shell of the DOS system. 1. When we execute 1.EXE directly in DOS, it is the running command that loads the program from 1.EXE into memory. 2. Command sets the CPU's CS:IP to point to the first instruction of the program (i.e., the entry point), allowing the program to run. 3. When the program finishes running, it returns to command.
4.9 Tracking the Program Execution Process
To observe the running process of the program, we can use debug. Debug can load the program into memory, set CS:IP to point to the entry of the program, but Debug does not relinquish control of the CPU, allowing us to use debug's related commands to execute the program step by step and see the execution results of each instruction.
Chapter 5 [BX] and LOOP Instructions
5.1 [BX]
To fully describe a memory unit, we need two pieces of information: 1. The address of the memory unit. 2. The length (type) of the memory unit. When we use [0] to represent a memory unit, 0 indicates the offset address, with the segment address defaulting to DS. The length (type) of the unit can be indicated by other operands in the instruction (e.g., registers) such as AX, AL.
5.2 LOOP Instruction
The format of the instruction is: LOOP label. When the CPU executes the LOOP instruction, it performs two operations: 1. (CX) <-- (CX) - 1 2. Checks the value in CX; if it is not zero, it jumps to the label to execute the program; if it is zero, it continues executing downwards. From the above description, we can see that the value in CX affects the execution result of the LOOP instruction. Typically, we use the LOOP instruction to implement loops, with CX storing the number of iterations. 1. Label In assembly language, a label represents an address. The three key points for using the LOOP instruction with CX to achieve looping functionality are: 1. Store the number of iterations in CX. 2. The address of the label where the LOOP instruction is located must be in front. 3. The program segment to be executed in a loop should be written between the label and the LOOP instruction. The framework is as follows: MOV CX, number of iterations Loop executing program segment LOOP label.
5.3 Tracking the LOOP Program in Debug
debug G can also be P.
5.4 Different Handling of Instructions by Debug and Assembly Compiler MASM
5.5 Combined Application of LOOP and [BX]
The variable X representing the offset address of the memory unit should be a variable because during the process of looping, the offset address must be able to increment. Therefore, we cannot use a constant to represent the offset address in the instruction; we can put the offset address into BX and access the memory unit using [BX]. In actual programming, we often encounter the problem of processing numbers in consecutive memory units using the same method. We need to use a loop to solve such problems, and we must be able to change the address of the memory unit to be accessed in the same way during each loop. Therefore, we cannot use a constant to specify the address of the memory unit but should use a variable.
5.6 Segment Prefix
In the instruction MOV AX, [BX], the offset address of the memory unit is given by BX, while the segment address defaults to DS. We can explicitly specify the segment address of the memory unit in the instructions that access memory units. These appear in the instructions that access memory units to explicitly indicate the segment address of the memory unit: "DS:" "CS:" "ES:" "SS:" are called segment prefixes in assembly language.
5.7 A Safe Space
In 8086 mode, writing content to a segment of memory space at will is very dangerous because this space may contain important system data or code. We seem to face a choice: to program safely and properly in the operating system, or to freely and directly manipulate real hardware using assembly language, understanding the truths that have long been masked by layers of system software. Note: We can directly manipulate real hardware using assembly language under DOS, as the running CPU in real mode DOS does not have the ability to comprehensively and strictly manage the hardware system. In general PCs under DOS, the DOS mode and other legitimate programs usually do not use the 256 bytes of memory space from 0:200 - 0:2FF, so using this space is safe.
5.8 Use of Segment Prefixes
Chapter 6 Programs with Multiple Segments
6.1 Using Data in the Code Segment
To explain, "DW" means define word type data, which can be said to define data or open up memory space. Here, we use DW to define 8 word-type data (separated by commas), with a total memory space of 16 bytes. Since they are in the code segment, when the program runs, the segment address of the code segment is stored in CS, so we can get their segment address from CS. Since the data defined by DW is at the very beginning of the code segment, the offset addresses are 0, 2, 4, 6, 8, A, C, E. How can this program be made to run directly in the system after compilation? We can specify the entry point of the program in the source program. We added a label "start" before the first instruction of the program, and this label appears after the pseudo-instruction end. The end not only informs the compiler that the program has ended but also tells the compiler where the entry point of the program is.
6.2 Using Stack in the Code Segment
When the program runs, the defined data is stored in CS:0000 - CS:000F, a total of 8 word units. We push the data from these 8 word units onto the stack in order and then pop them back to these 8 word units in reverse order, thus achieving reverse storage of data. The problem is that we must first have a segment of memory that can be used as a stack. As mentioned earlier, this space should be allocated by the system. We can obtain a segment of space by defining data in the program and then use this segment of space as stack space.
6.3 Putting Data, Code, and Stack into Different Segments
In the previous sections, we used data and stack in the program, and we placed data, stack, and code all in one segment. We need to pay attention to where the data is, where the stack is, and where the code is when programming. Doing so clearly has two problems: 1. Putting them all in one segment makes the program seem chaotic. 2. In the previous program, the amount of data processed was small, and the occupied space was small, so it was not a problem to put them in one segment. But if the space required for data, stack, and code exceeds 64KB, they cannot be placed in one segment. We can define multiple segments in the same way we defined the code segment, and then define the necessary data in those segments or obtain stack space by defining data. The references to segment names in the program will be processed by the compiler as a value representing the segment address. The pseudo-instruction ASSUME associates CS, DS, and SS with CODE, DATA, and STACK respectively. After doing this, the CPU will...
Chapter 7 More Flexible Memory Addressing
7.1 AND and OR Commands
AND instruction: logical AND instruction, performing bitwise AND operation. This instruction can set the corresponding bit of the object to 0 while keeping other bits unchanged. OR instruction: logical OR instruction, performing bitwise OR operation. This instruction can set the corresponding bit of the object to 1 while keeping other bits unchanged.
7.2 About ASCII Code
There are many encoding schemes in the world, one of which is ASCII code, commonly used in computer systems. Simply put, an encoding scheme is a set of rules that specify what kind of information is used to represent real objects. In the process of text editing, encoding and decoding according to ASCII encoding rules are involved.
7.3 Data Given in Character Form
DB 'unix'
7.4 Case Conversion Issues
For a letter, regardless of whether it is originally uppercase or lowercase, if we set its 5th bit to 0, it will become an uppercase letter. If we set its 5th bit to 1, it will become a lowercase letter.
7.5 [BX + IDATA]
[BX + IDATA] represents a memory unit whose offset address is (BX) + IDATA. MOV AX, [BX + IDATA] MOV AX, [IDATA + BX] MOV AX, IDATA[BX] MOV AX, [BX].IDATA
7.6 Processing Arrays with [BX + IDATA]
With the representation of memory units as [BX + IDATA], we can view the data we need to process as more advanced structures. We can treat these two strings as two arrays, one starting at address 0 and the other starting at address 5. Therefore, we can use [0 + BX] and [5 + BX] to locate the characters of these two strings in the same loop. Here, 0 and 5 provide the starting offset addresses for the two strings, while BX provides the relative address starting from the starting offset address. The starting addresses of these two strings in memory are different, but the relative addresses of each character from the starting address change in the same way. C language addressing method A[i], B[i]. Assembly addressing method 0[BX], 5[BX]. The method of [BX + IDATA] provides a convenient mechanism for implementing arrays in high-level languages.
7.7 SI and DI
SI and DI are registers in the 8086 CPU that are similar in function to BX, but SI and DI cannot be divided into two 8-bit registers for use. MOV AX, [BX] MOV AX, [SI] MOV AX, [DI] MOV AX, [BX + 123] MOV AX, [SI + 123] MOV AX, [DI + 123]
7.8 [BX + SI] and [BX + DI]
Let's analyze the instruction MOV AX, [BX + SI]: it moves the contents of a memory unit into AX, where this memory unit's length is 2 bytes (word unit), and the offset address is ((BX) + (SI)), with the segment address in DS. It can also be written as MOV AX, [BX][SI].
7.9 [BX + SI + IDATA] and [BX + DI + IDATA]
MOV AX, [BX + SI + IDATA] MOV AX, [BX + IDATA + SI] MOV AX, IDATA[BX][SI] MOV AX, [BX].IDATA[SI] MOV AX, [BX][SI].IDATA
7.10 Flexible Use of Different Addressing Methods
(1) [IDATA] uses a constant to represent the address, which can be used to directly locate a memory unit. (2) [BX] uses a variable to represent the address, which can be used for indirect addressing of a memory unit. (3) [BX + IDATA] uses a variable and a constant to represent the address, which can indirectly point to a memory unit based on a starting address using a variable. (4) [BX + SI] uses two variables to represent the address. (5) [BX + SI + IDATA] uses two variables and one constant to represent the address. This allows us to view the data we need to process from a more structured perspective.
Chapter 8 Two Basic Issues in Data Processing
8.1 BX, SI, DI, BP
1. Where is the data being processed? 2. How long is the data being processed? These two issues must be clearly or implicitly stated in machine instructions; otherwise, the computer cannot work. 1. In the 8086 CPU, only four registers (BX, BP, SI, DI) can be used in "[]" for addressing memory units. 2. In "[]", these four registers (BX, BP, SI, DI) can exist individually or only appear in four combinations: BX(SI, DI) BP(SI, DI). 3. Whenever a register BP is used in "[]", and the instruction does not explicitly provide a segment address, the segment address defaults to SS.
8.2 The Location of Data Processed by Machine Instructions
The vast majority of machine instructions are data processing instructions, which can be roughly divided into three categories: reading, writing, and computing. At the machine instruction level, we do not care about the value of the data; we care about the location of the data to be processed just before the instruction is executed. The data to be processed can be located in three places: inside the CPU, in memory, or in ports.
8.3 Expression of Data Location in Assembly Language
1. Immediate Data (IDATA) Directly included in machine instructions (in the CPU's instruction buffer before execution), referred to as immediate data (IDATA) in assembly language. MOV AX, 0001H ==> B80100. 2. Register The data to be processed is in the register, and the corresponding register name is given in the assembly instruction. MOV AX, BX ==> 89DB. 3. Segment Address (SA) and Offset Address (EA) The data to be processed is in memory, and the EA can be given in assembly instructions in the format [BX], while SA can be in a certain segment register. The register storing the segment address can be defaulted or explicitly provided through adding segment prefix.
8.4 Addressing Methods
When data is stored in memory, we can specify the offset address of this memory unit using various methods. This method of locating memory units is generally referred to as addressing methods: Direct Addressing, Register Indirect Addressing, Register Relative Addressing, Base-Index Addressing, Base-Index Relative Addressing.
8.5 How Long is the Data to be Processed by the Instruction
The instructions of the 8086 CPU can process two sizes of data: BYTE and WORD. Therefore, in machine instructions, it is necessary to specify whether the operation is a word operation or a byte operation. 1. Specify the size of the data to be processed through the registers. 2. In the absence of the register name, specify the length of the memory unit using the operator PTR, BYTE PTR, WORD PTR. 3. Other methods. Some instructions default to access word units or byte units, such as PUSH and POP.
8.6 Comprehensive Application of Addressing Methods
A structured data set contains multiple data items, and the types of these data items are different; some are word-type data, some are byte-type data, and some are arrays. Generally, we can use the method [BX + IDATA + SI] to access the data in the structure. ** For example, using BX to locate the starting address of the entire structure, using IDATA to locate a certain data item in the structure, and using SI to locate each element in that data item. In C language, we see something like dec.cp[i]. dec is a variable name indicating the address of the structure variable, cp is a name indicating the address of the data item cp, and i is used to locate each element in cp. In assembly language, the approach is: BX.10H[SI].
8.7 DIV Instruction
DIV (division) instruction, division instruction. Divisor: 8-bit or 16-bit, in a register or memory unit. Dividend: (default) stored in AX or DX and AX. Result: 8-bit AL, 16-bit AX. Quotient: AL, AX. Remainder: AH, DX. Instruction format: div reg, div memory unit. DIV BYTE PTR DS:[0], DIV WORD PTR DS:[0]. Using the division instruction to calculate 100001 / 100, using the division instruction to calculate 1001 / 100.