Acquiring a Domestic Open Source Logic Analyzer

Recently, I acquired a domestic open-source logic analyzer: the PX Logic logic analyzer produced by Octopus.This logic analyzer focuses on high-speed acquisition, with the following performance specifications:• Maximum 32-channel logic analyzer• In buffer mode, supports up to 8 channels at 1G, total bandwidth 8G, storage depth 4Gbits• Under USB3.0 stream mode, supports up to 2 channels at 1G, total bandwidth 2G, storage depth 1024Gbits• Sampling via USB3.0 for transmission, compatible with USB2.0• Input sampling threshold adjustable from 0-6V• Open-source decoding protocol library with over 200 protocols, developed using Python, allowing for custom developmentThe core hardware components use domestic devices:USB3.0 PHY uses the WCH569W from Nanjing Qinheng MicroelectronicsFPGA uses the domestic FPGA PGL22G from UnisocThe buffer mode means that it has built-in buffering, allowing the collected signals to be directly transmitted and stored internally; the amount of data stored depends on the current sampling quantity and the size of the onboard memory; stream mode means that the currently sampled data can be sent to the computer at any time, theoretically allowing continuous sampling as long as your computer’s performance is sufficient.I acquired the mid-range 16-channel model priced at 599:

Just had a compatibility issue, used this to capture the SPD waveform:This product is very useful for analyzing motherboard timing, and I will further research and attempt to write decoding functions to support more buses.