FPGA: The Core Engine of LiDAR

When Velodyne’s LiDAR made its debut at the 2007 DARPA Grand Challenge, it not only opened a new chapter in autonomous driving but also revealed a transformation in sensor data processing paradigms. Within the complex internal world of LiDAR, FPGA (Field-Programmable Gate Array) has quietly replaced traditional CPUs as the main control unit, becoming the “digital heart” that supports this precision optical instrument. This shift is driven by the perfect combination of two core advantages: the flexibility to adapt algorithms for rapid iteration and the extreme efficiency brought by dedicated circuits.

1. The Computational Dilemma of LiDAR: The Pitfalls of CPU Generality

The workload of LiDAR far exceeds the comfort zone of general-purpose processors:

Massive Real-Time Signal Processing: Millions or even tens of millions of laser reflection points need to be processed every second. Each point contains multi-dimensional information such as flight time, intensity, and orientation, requiring real-time waveform analysis, noise filtering, and distance calculation.
High-Precision Timing Control: Laser pulse emissions require nanosecond-level precision control; the synchronization of high-speed rotation or MEMS mirrors requires strict timing management.
Complex Environmental Perception Algorithms: Distinguishing real obstacles from rain and fog interference, recognizing low-reflectivity objects, and processing multiple reflection signals (such as echoes after penetrating leaves).

The bottlenecks of CPUs are evident:

Von Neumann Architecture Constraints: Sequential execution of instructions creates a significant bottleneck when faced with massive parallel data streams (such as tens of thousands of channels of reflected waves arriving simultaneously).
Low Compute/Power Ratio: The complex pipelines and cache hierarchies designed for generality are inefficient when processing highly structured radar data, making it difficult to meet the stringent power requirements of automotive environments.
Real-Time Guarantees Are Challenging: Delays caused by operating system scheduling and interrupt responses introduce uncertainty, posing high risks in control tasks that require strict timing guarantees.

2. FPGA’s Solution: The Ingenious Balance of Dedicated Circuits and Programmability

The essence of FPGA is a blank digital circuit board that can be “drawn” by engineers on-site:

Hardware-Level Parallel Architecture:

It contains thousands of programmable logic blocks (CLBs), dedicated DSP slices, high-speed block RAM, and abundant I/O resources.
Key Advantage: It can construct dozens or even hundreds of independent data processing pipelines. For example, assigning a dedicated processing channel for each laser echo signal enables true parallel computation, resulting in an order of magnitude increase in throughput.

The Flexibility of “Software-Defined Hardware”:

Programming is done using hardware description languages (HDLs) like VHDL/Verilog, which essentially configures the hardware circuit structure.
Key Advantage: Algorithms are hardware! Engineers can customize the design of the most suitable computational units (such as optimized FFT cores, peak detection circuits, and filter chains) based on the current optimal algorithms. Dedicated circuits eliminate the overhead of CPU general instruction sets, resulting in extremely high efficiency.

Nanosecond-Level Deterministic Delay:

Once the circuit is programmed, the signal path is fixed, and execution time is strictly predictable.
Key Advantage: Perfectly meets the stringent timing accuracy requirements for tasks such as laser emission control, motor drive, and data acquisition synchronization (with errors often in the nanosecond range).

Case Study: Efficient Implementation of Echo Waveform Processing with FPGA

The “complex echo” scenario described by users (as shown in the figure below) is highly challenging:

Complexity of the Problem: A single emission may receive multiple superimposed echoes from objects at different distances and reflectivity (such as multiple reflections after penetrating leaves), where the waveform is no longer an ideal pulse but may be a continuous, distorted signal.
Core Processing Tasks:

Accurate Distance Measurement: Precisely identifying the arrival time of each valid echo within the complex waveform.
Reflectivity Calculation: Accurately extracting the intensity (amplitude) of each echo to infer the reflective characteristics of the object.
Noise Suppression: Filtering out interference from ambient light, circuit noise, etc.

FPGA Dedicated Circuit Solution:

High-Speed ADC Acquisition: FPGA directly drives high-sampling-rate ADCs (up to several GSPS) to capture raw waveform data.
Parallel Preprocessing Pipeline:

Dedicated Filtering Circuits: Real-time digital filtering (such as FIR, IIR) to suppress background noise.
Peak Detection Array: Deploying multiple parallel “peak detection engines”. Each engine uses optimized threshold comparison and sliding window maximum detection hardware logic to concurrently scan waveform data, quickly locating all potential echo peak points and their timestamps.
Waveform Feature Extraction Unit: For each detected peak area, the hardware calculates features such as rising edge slope, pulse width, and energy integral.

Intelligent Decision Logic: Based on the extracted features, customized algorithms (such as adaptive thresholds and waveform matching templates) distinguish real target echoes from noise and multiple reflections, accurately calculating distance and reflectivity.

Result Packaging Output: The processed point cloud data is sent to the domain controller via high-speed interfaces (such as Ethernet, PCIe).

Efficiency Comparison: CPUs need to process massive sampling points through software loops on general ALUs, resulting in low efficiency and significant delay fluctuations. FPGAs solidify the entire processing flow in parallel hardware pipelines, completing calculations as data “flows” through, resulting in extremely low latency, massive throughput, and significant power optimization.

3. Rapid Iteration: The Core Value of FPGA During Technological Evolution

LiDAR has been on vehicles for just over a decade (from 2007 Velodyne @ DARPA to now), and both hardware architecture and core algorithms are still evolving rapidly:

Rapid Algorithm Evolution: Anti-interference algorithms, point cloud segmentation, motion compensation, solid-state scanning solutions, etc., are continuously iterating.
Hardware Platform Updates: New types of detectors, light sources, and scanning mechanisms are constantly emerging.

FPGA’s Irreplaceable Iteration Advantage:

On-Site Reconfiguration Capability: Discover an algorithm flaw or need an upgrade? No need to change the PCB! By updating the FPGA configuration file (bitstream), the “hardware circuit” can be redeployed within minutes. This is much more agile than re-spinning ASICs (which take months and cost millions of dollars) or waiting for lengthy CPU software OTA updates.
Agile Development Verification: Using HDLs and high-level synthesis tools (HLS), algorithm engineers can quickly turn new ideas into hardware prototypes, validating performance on real hardware and significantly accelerating the development cycle.
Platform Compatibility: The same FPGA can be reprogrammed to adapt to different models of detectors, motor drive interfaces, or communication protocols, enhancing hardware platform reusability.

The Dilemma of ASICs: Although ultimate efficiency may be higher, the high NRE costs (ranging from millions to tens of millions of dollars) and long manufacturing cycles of 12-24 months pose significant risks in the current landscape of LiDAR technology, where the technical route has not fully converged and algorithms are rapidly evolving. FPGA is the optimal solution during the exploratory phase of technology, balancing high performance and flexibility.

4. Future Outlook: The Continuous Evolution and Ecological Expansion of FPGA

The position of FPGA in LiDAR remains solid and continues to evolve:

Increased Integration: Modern FPGAs integrate multi-core ARM processors (such as Xilinx Zynq UltraScale+, Intel Agilex SoC), forming a heterogeneous computing platform. Complex control logic and protocol stacks run on CPUs, while core signal processing and real-time control are efficiently executed by programmable logic, enhancing synergy.
Intelligent Toolchain: HLS (High-Level Synthesis) allows engineers to describe algorithm intentions using languages like C++/Python, with tools automatically generating optimized RTL code, significantly lowering the hardware development threshold.
AI Empowerment: FPGAs are beginning to integrate dedicated AI engines (such as AI Tensor Blocks), providing hardware acceleration possibilities for real-time deep learning preprocessing in LiDAR point clouds (such as dynamic target recognition and semantic segmentation).
Automotive Grade Reliability: Major FPGA suppliers (Xilinx/AMD, Intel/Altera, Lattice) offer automotive-grade devices certified by AEC-Q100, meeting the stringent requirements of automotive environments (temperature, vibration, lifespan).

Conclusion

In the critical fifteen years of LiDAR transitioning from the laboratory to mass production, FPGA has perfectly addressed the dual challenges of high real-time signal processing and rapid technological iteration with its extreme efficiency of “implementing software algorithms in hardware” and amazing flexibility of “defining hardware functions with software”. It is not just the main control chip of LiDAR but also the core engine of its perception capabilities. As autonomous driving advances to higher levels, LiDAR will need to process denser point clouds and run more complex algorithms, and FPGA, as the foundational technology supporting this evolution, will only become more valuable. When a beam of laser light strikes an unknown environment, it is the dedicated circuits built by FPGA that transform chaotic light signals into precise perception data streams in nanoseconds, illuminating the path forward for intelligent driving.

The Essence of Technology: The success of FPGA in LiDAR is a model of the concept of “Software Hardening”—executing computation-intensive, real-time core algorithms on dedicated hardware circuits tailored for them, rather than in the software world of general CPUs, thereby releasing an order of magnitude improvement in performance-to-power ratio while retaining the critical plasticity to respond to future changes.