This article takes the Cortex-A53 processor as an example, accessing the internal storage units (tag RAM and dirty RAM) in the processor to read the MOESI information in the cache line. The Cortex-A53 provides a mechanism to access some internal storage units used by the Cache and TLB by reading certain system registers. This feature … Read more
Click the card below to follow Arm Technology Academy This article is organized by the WeChat public account Arm Selected, and mainly shares the related content of Armv8 Cache Coherency Solution: MOESI protocol. 1. MOESI State Definitions The Armv8 architecture uses the MOESI protocol to maintain data consistency between multiple cores. The MOESI protocol describes … Read more
1. MOESI State Definitions The ARMv8 architecture uses the MOESI protocol to maintain data consistency across multiple cores. The MOESI protocol describes the state of a shared cache line in L1 Data Cache as follows: M, Modified, Unique Dirty, only exists in the current cache (unique) and the data in this cache line is different … Read more