This article takes the Cortex-A53 processor as an example, accessing the internal storage units (tag RAM and dirty RAM) in the processor to read the MOESI information in the cache line. The Cortex-A53 provides a mechanism to access some internal storage units used by the Cache and TLB by reading certain system registers. This feature … Read more
Click the card below to follow Arm Technology Academy This article is selected from the Jishu column “Arm Selection” and will briefly discuss how beginners can efficiently learn about Arm v8/Arm v9 architecture. Do you want to get rich overnight? Have lots of money, buy many houses, have a relaxed job with no pressure, avoid … Read more
Click the card below to follow Arm Technology Academy This article is organized by the WeChat public account Arm Selected, and mainly shares the related content of Armv8 Cache Coherency Solution: MOESI protocol. 1. MOESI State Definitions The Armv8 architecture uses the MOESI protocol to maintain data consistency between multiple cores. The MOESI protocol describes … Read more
Introduction to Cache Cache is a block of memory in ARM that can be accessed at high speed. Each cache block contains: 1. Main memory address information; 2. Cached data. Cache can significantly increase the average speed of memory access. Cache has the following two characteristics: 1. Access locations are spatially limited. An access to … Read more
1. Pseudo-LRU and LRU Cache replacement strategies are used to determine which cache items should be replaced when the cache space is full. Pseudo-LRU (Pseudo-Least Recently Used) and LRU (Least Recently Used) are both common cache replacement strategies, and they have the following differences: Principle: LRU: The LRU strategy determines the usage frequency of cache … Read more
Beginners often struggle to form a systematic understanding when learning about Cache. While certain concepts may be clear, the specific process of Cache read and write operations can be confusing. This video tutorial aims to clarify this issue. The MPU and Cache are also core topics in learning about the M7 core chip. Tencent Video: … Read more
Click the blue "Arm Selected" in the top left corner and select "Set as Favorite" Table of Contents 1. Why Use Cache? 2. Background: Changes in Architecture? 3. Cache Hierarchy – Big.LITTLE Architecture (Example: A53) 4. Cache Hierarchy – DynamIQ Architecture (Example: A76) 5. What Are the Sizes of L1/L2/L3 Cache? 6. Introduction to Cache-Related … Read more
Author’s Note：Many readers have previously consulted me about the MPU and Cache usage related issues of the NXP S32K3xx series MCUs. The performance of a powerful dual-issue high-performance CPU core like the Cortex-M7 is often limited by the on-chip Embedded Flash (eFlash, with a working frequency ≤50MHz) when operating at high speeds (Core clock ≥150MHz), … Read more
Click on the above“Mechanical and Electronic Engineering Technology” to follow us In the world of electronic products, chips are like the heart, pulsating with the rhythm of digits. Understanding chip performance metrics is key to choosing the right electronic product. Today, we will delve into the three core performance metrics of chips—clock speed, process technology, … Read more
1 What is eMMC eMMC stands for embedded MultiMediaCard, which is a standard for flash memory cards that defines the physical architecture and access interface and protocol for storage systems based on embedded MultiMediaCard, specifically established and published by the JEDEC (Joint Electron Device Engineering Council).It is an extension of MMC with advantages such as … Read more