Introduction to eMMC Technology

Introduction to eMMC Technology

1 What is eMMC eMMC stands for embedded MultiMediaCard, which is a standard for flash memory cards that defines the physical architecture and access interface and protocol for storage systems based on embedded MultiMediaCard, specifically established and published by the JEDEC (Joint Electron Device Engineering Council).It is an extension of MMC with advantages such as … Read more

vLLM Framework Source Code Analysis: Block Allocation and Management

vLLM Framework Source Code Analysis: Block Allocation and Management

1. Block Overview A significant innovation of vLLM is the division of the physical layer GPU and CPU available memory into several blocks, which effectively reduces memory fragmentation issues. Specifically, vLLM’s blocks are divided into logical and physical levels, with a mapping relationship between the two. The following diagram explains the relationship between the two … Read more

Annual Highlights | CPU Cache/Embedded Open Source Projects/SoC Multi-core Boot

Annual Highlights | CPU Cache/Embedded Open Source Projects/SoC Multi-core Boot

Click on the card below to follow Arm Technology Academy 2023 Annual Review Time flies, and before we know it, it’s the end of the year again. In 2023, Arm Technology Academy published over 400 technical articles covering various technology fields. Thank you for your continued support. To help everyone learn and grow, we have … Read more

Understanding ARM Cortex-M7 Cache: Basics and Principles

Understanding ARM Cortex-M7 Cache: Basics and Principles

Summary Introduction 1. Why introduce cache in CPU architecture? 2. The role of cache 3. Memory system of ARM Cortex-M4 / Cortex-M7 CPU architecture 4. Detailed explanation of basic concepts related to cache Conclusion Introduction For many years, most embedded MCUs based on RISC CPU (like 8051 core, PIC core, and ARM Cortex M0/M0+ and … Read more

Understanding the Architecture of Arm Cortex-A53 Cache

Understanding the Architecture of Arm Cortex-A53 Cache

Click on the card below to follow Arm Technology Academy This article is authorized and reprinted from the WeChat public account Arm Selected. This article mainly shares the architecture interpretation of A53 cache. 1 A53 uses the classic big-LITTLE architecture Below is an early classic big-LITTLE architecture diagram. Figure 1 Figure 2 2 A53’s cache … Read more