1. MOESI State Definitions The ARMv8 architecture uses the MOESI protocol to maintain data consistency across multiple cores. The MOESI protocol describes the state of a shared cache line in L1 Data Cache as follows: M, Modified, Unique Dirty, only exists in the current cache (unique) and the data in this cache line is different … Read more
Click the card below to follow Arm Technology Academy This article is selected from the “Arm Technology Blog” column of the Jishu Community, authored by RC. This article mainly helps to understand the Armv8 memory system. Original link: https://stdrc.cc/post/2021/08/23/armv8-memory-system/ Cache coherency Cacheability Normal memory can be set as cacheable or non-cacheable, and can be set … Read more
Cache coherency Cacheability Normal memory can be set as cacheable or non-cacheable, and can be set separately for inner and outer. Shareability If set to non-shareable, that segment of memory is only used by a specific core. If set to inner shareable or outer shareable, it can be accessed by other observers (other cores, GPU, … Read more
Many people have heard of the term cache coherency, but do not fully understand the considerations for System-on-Chip (SoC) devices, especially those using Network-on-Chip (NoC). To understand the current issues, one must first grasp the role of cache in the memory hierarchy. Cache in Memory Hierarchy The CPU has relatively few extremely fast registers. The … Read more