In chip design, power consumption optimization is a key factor determining chip performance, battery life, heat dissipation, and cost. The sources of power consumption mainly involve power supply voltage, clock frequency, number of devices, and process technology (which affects threshold voltage and leakage current). From the composition of power consumption, we can optimize at different … Read more
Before making a decision, hesitation may be necessary. However, once a decision is made, one should move forward without looking back. ― ― Dazuo Ishikawa Unknowingly, I have written several articles on the topic of SoC power consumption, so let’s summarize them. SoC Design Power Consumption — Introduction SoC Design Power Consumption — Clock Gating … Read more
In multi-voltage design, isolation cells are often used; this article briefly introduces what an iso cell is, how to use an iso cell, when to add an iso cell, and the insertion location of the iso cell. 1. What is an iso cell? Isolation cell (隔离单元) is typically used in power shutdown technology (PSO) and … Read more
Hello everyone, I am “Da Yi Zong”. Today we are going to talk about low power design techniques, which are key to ensuring the continuous operation of embedded systems. Whether it is a microcontroller (MCU) or a PLC, properly utilizing low power modes can greatly extend the battery life of devices. What is a low … Read more
Hello everyone, I am Da Yi! Today, let’s talk about the techniques for low power design of microcontrollers. The power design of microcontrollers is not only closely related to energy saving and environmental protection but is also particularly important for portable devices powered by batteries. So how can we reduce the power consumption of microcontrollers? … Read more
In the previous article, we introduced methods forsystem-level low power design, such ashardware-software co-design,power management mechanisms, etc. This issue will delve into the core technologies ofarchitecture-level low power design, includingmulti-voltage design (Multi-VDD),dynamic voltage frequency scaling (DVFS),system clock optimization,asynchronous design, andalgorithm optimization. By reasonably dividing power supply areas, dynamically adjusting voltage and frequency, and optimizing clock … Read more
Recently, I have been reading “The Art of Hardware Architecture”, and this blog post is also derived from the content in the book. With the advancement of technology, low-power design has become increasingly important.As a digital front-end designer, let’s take a look at how to reduce power consumption at the RTL level. In large-scale ASIC … Read more
To better serve everyone, I would like to report on the main business currently handled by me. For design outsourcing, friends with backend outsourcing needs are welcome to contact me (WeChat ID: ic-backend2018), and of course, if you have resources, you can also introduce them to me, and there will definitely be generous cash rewards … Read more
Welcome FPGA engineers to join the official WeChat technical group ClickBlue TextFollow us at FPGA Home – the best and largest pure engineer community in China for FPGA This article mainly introduces the power design for Xilinx FPGA, covering types of power supply, voltage requirements, power consumption needs, power-up and power-down timing requirements, and common … Read more
The following question was asked by a VIP student from the Cortex-A72 training camp: After completing the single-core CPU PR, how do I output the data to TOP for multi-core hierarchy integration? Answer: After completing the single-core CPU, you need to output library files such as SDC, DEF, LEF, GDS, Netlist, LIB, etc., and then … Read more