During the process of FPGA design, it is common to encounter warnings during compilation indicating that some latches have been generated. Generally, the design rules for FPGAs also advise against the generation of latches. So, what exactly is a latch? And how can we avoid the occurrence of latches in FPGA design?1 Comparison of Latches, Flip-Flops, and Registers(1) LatchA latch is a level-triggered storage unit, where the action of data storage (state transition) depends on the level of the input clock (or enable) signal. The output only changes with data input when the latch is in the enabled state.There are ordinary latches and gated latches. An ordinary latch has no control signal, and its output state is always directly determined by the input. In practical digital systems, a specific control signal is often needed to coordinate the timing of the latch’s state transitions. When the control signal is inactive, the output remains unchanged and does not vary with the input; when the control signal is active, the output is determined by the input and follows its changes.① Because a gated latch can receive input signals during the active period of the control signal, any change in the input signal will directly cause a change in the latch’s output state. If the input signal changes multiple times, the output state may also change multiple times, a phenomenon known as latch flipping.② Furthermore, when the control signal of a gated latch is active, the latch behaves like a combinational circuit, and the model of the sequential logic circuit becomes equivalent to a feedback system of two combinational circuits. Therefore, the system may become unstable due to transient characteristics, leading to oscillation phenomena.(2) Flip-FlopA flip-flop is an edge-sensitive storage unit, where the action of data storage (state transition) is synchronized by the rising or falling edge of a signal (restricting the state transition of the storage unit to a very short time). (The clocked D flip-flop is actually a D latch, while the edge-triggered D flip-flop is the true D flip-flop.)Flip-flops are divided into two types: master-slave flip-flops and edge-triggered flip-flops. The master-slave flip-flop receives data during the active period of the clock (master flip-flop) and outputs state transitions at the clock edge. Edge-triggered flip-flops only receive data and change output states during the clock edge. Currently, master-slave flip-flops are rarely seen, and most practical applications use edge-triggered flip-flops.(3) RegisterA register is used to temporarily store data involved in computations and the results of those computations. In practical digital systems, a synchronous sequential logic circuit that can store a set of binary codes is referred to as a register.Differences and Connections: Since flip-flops have memory functions, they can be easily used to construct registers. A single flip-flop can store one bit of binary code, so connecting the clock ports of n flip-flops together can form a register that stores n bits of binary code.From the perspective of data storage, the functions of registers and latches are the same; their difference lies in that registers are controlled by synchronous clocks, while latches are controlled by level signals. The general design rule is to avoid generating latches in most designs. They can ruin the timing of your design and are often very subtle, making them hard to detect for inexperienced designers.2 Characteristics of Latches(1) Sensitive to Glitches (When the enable signal is active, the output state may change multiple times with the input, causing flipping, which is dangerous for the next circuit), cannot be asynchronously reset, thus remaining in an uncertain state after power-up.(2) Latches complicate static timing analysis and lack reusability. (First, latches do not participate in clock signal transmission, making STA impossible; second, synthesis tools may optimize away latches, leading to inconsistent simulation results.)(3) The basic units in FPGAs are composed of lookup tables and flip-flops. If latches are generated, more resources are required. Based on the characteristics of latches, it is evident that caution is needed in circuit design. If the synthesis process generates latches that do not align with design intentions, it will lead to design errors, including simulation and synthesis issues. Therefore, unexpected latches should be avoided in design. If combinational logic statements do not use any always blocks, it can ensure that the synthesizer will not synthesize latches.(4) However, if both latches and flip-flops are constructed using NAND gates, the logic resources consumed by latches are fewer than those of D flip-flops (D flip-flops require 12 MOS transistors, while latches only require 6 MOS transistors), making latches more integrated.Thus, latches are used in ASIC design. However, latches are sensitive to glitches, lack asynchronous reset, and cannot ensure that the chip is in a defined state upon power-up. Additionally, latches complicate static timing analysis and hinder design reusability. Therefore, in ASIC design, except for high-speed circuits like CPUs or area-sensitive circuits like RAM, the use of latches is generally not recommended.3 The Emergence of Latches and SolutionsIn combinational logic descriptions based on always statements, latches are often synthesized due to incomplete descriptions in if and case statements, leading to latch functionality during synthesis. For example, when writing a decoder with input a and output b, where a is a 2-bit input and b is an 8-bit output, if written as follows:always@( * ) case(a) 2’b00: b = 8’d1; 2’b01: b = 8’d5; 2’b10: b = 8’d8; 2’b11: b = 8’d17; endcase However, if the bit width of a is changed to 3, as follows:always@( * )case(a) 3’b000: b = 8’d1; 3’b001: b = 8’d5; 3’b010: b = 8’d8; 3’b011: b = 8’d17; endcaseIt can be seen that the second synthesis diagram has generated a latch. However, the only difference between the two pieces of code is that the bit width of a changed from 2 to 3. Why is this the case?This is due to the incomplete description of the case statement. In the first piece of code, all four possible values of input a are enumerated, so it is a complete description. In the second piece of code, a has become a 3-bit number, and only the values 3’b000, 3’b001, 3’b010, and 3’b011 are listed, while the values from 3’b100 to 3’b111 are not enumerated. Although these unlisted values will not appear during actual execution, the system does not know this during compilation, so it will latch the output b when values from 3’b100 to 3’b111 appear, resulting in latch functionality.The main reason for avoiding the occurrence of latches in hardware design is that latches can produce glitches, which are dangerous for the next circuit. Additionally, their subtlety makes them hard to detect. Therefore, latches should be avoided in design as much as possible.To prevent the occurrence of latches, it is essential to ensure complete descriptions for if statements and case statements, with the most common method being to always include else and default.Summary:The fundamental reason for the generation of latches: When combinational logic needs to hold, latches will be synthesized.The hazards of latches:(1) Latches can produce glitches, which are dangerous for the next circuit;(2) They cannot be asynchronously reset, thus remaining in an uncertain state after power-up;(3) Latches complicate static timing analysis and lack reusability.