In-Depth Analysis of Linux NUMA Systems: From Principles to Practice

In-Depth Analysis of Linux NUMA Systems: From Principles to Practice

In-Depth Analysis of Linux NUMA Systems: From Principles to Practice 1 Overview of NUMA Systems 1.1 What is NUMA? Non-Uniform Memory Access (NUMA) is a memory architecture designed for multiprocessor systems. In traditional Symmetric Multiprocessing (SMP) systems, all processors share a single centralized memory controller, and all memory accesses have the same latency, a structure … Read more

RISC-V Architecture 64-Core CPU Performance Testing

RISC-V Architecture 64-Core CPU Performance Testing

The SG2042 uses the T-head Xuantie C910 core. It has a clock speed of 2.0GHz, with a total of 64 cores, where every 16 cores form a NUMA node, and there are 4 memory channels. The following tests were conducted using the vendor-provided GCC 10.2 version on an Ubuntu system with SSH remote access. In … Read more

Methods to View CPU Instruction Set in Linux and Configure NUMA Functionality

Methods to View CPU Instruction Set in Linux and Configure NUMA Functionality

1. What is a CPU Instruction Set The CPU instruction set is a collection of basic instructions stored within the CPU, which defines all operations that the CPU can execute. It is a list of inherent hardware functionalities of the CPU and serves as a bridge for communication between software and hardware. It is important … Read more

Common GDB Commands for Linux

Common GDB Commands for Linux

1. Common GDB Commands 1. Basic Commands 1.1. Start Debugging gdb test.elf 1.2. View Disassembly # Set style to view disassembly set disassembly-floavor intel disassemble # Disassemble current instruction disassemble $pc, $pc+0x100 1.3. View Functions info functions 1.4. Print Addresses # Print variable address Print function address print &var print test_function 1.5. GDB Remote Connection … Read more

Resource Allocation and Performance Optimization in x86 Server Virtualization

Resource Allocation and Performance Optimization in x86 Server Virtualization

Virtualization is a broad term that generally refers to the operation of computing components on a virtual rather than a physical basis. It is a solution aimed at simplifying management and optimizing resources. Server virtualization is a technology used to integrate x86-based servers to improve resource utilization and performance. This article focuses on analyzing the … Read more

NUMA-Aware Optimization of Sparse Matrix-Vector Multiplication on ARMv8-based Many-Core Architectures

NUMA-Aware Optimization of Sparse Matrix-Vector Multiplication on ARMv8-based Many-Core Architectures

Original Information Title: NUMA-Aware Optimization of Sparse Matrix-Vector Multiplication on ARMv8-based Many-Core Architectures Published Conference: The 17th Annual IFIP International Conference on Network and Parallel Computing (CCF Class C Conference) Author List 1) Yuxiaosong, China University of Petroleum (Beijing), School of Information Science and Engineering, Major in Computer Science and Technology, Graduate Class of 2019 … Read more

SylixOS Officially Supports Heterogeneous Computing (Big.LITTLE) Processors, Becoming the First Commercial Real-Time Operating System to Support Big.LITTLE Scheduling

SylixOS Officially Supports Heterogeneous Computing (Big.LITTLE) Processors, Becoming the First Commercial Real-Time Operating System to Support Big.LITTLE Scheduling

Heterogeneous Computing (Big.LITTLE) Processors During Intel’s 2021 Architecture Day event, the new generation of processors was first announced to utilize a heterogeneous core design (referred to as P-Core and E-Core by Intel) on the PC platform, similar to the ARM platform’s Big.LITTLE heterogeneous core mechanism. Intel named the “small core” as the Efficient-Core and the … Read more

3x Inference Acceleration on RISC-V CPU! V-SEEK: Accelerating 14B LLM on SOPHON SG2042

3x Inference Acceleration on RISC-V CPU! V-SEEK: Accelerating 14B LLM on SOPHON SG2042

Keywords: V-SEEK, LLM Inference Optimization, RISC-V, SOPHON SG2042, llama.cpp, NUMA Optimization V–SEEK: ACCELERATING LLM REASONING ON OPEN-HARDWARE SERVER-CLASS RISC-V PLATFORMS https://arxiv.org/abs/2503.17422 In recent years, the exponential growth of large language models (LLMs) has relied on GPU-based systems. However, CPUs are gradually becoming a flexible and cost-effective alternative, especially for inference (the phase where the model … Read more

The ‘Data War’ of Multicore Chips: What is the Cache Coherence Problem?

The 'Data War' of Multicore Chips: What is the Cache Coherence Problem?

Hello everyone, welcome to my column. In previous articles, we explored the benefits of Thread-Level Parallelism (TLP) and the classifications of TLP architectures. Today, let’s learn about the cache coherence problems faced by shared memory architectures. Table of Contents 1. Shared Memory Architecture 2. Cache Coherence Problems Table of Content Mind Map 01Shared Memory ArchitectureShared … Read more

Understanding the Relationship Between Linux Threads, Cores, and CPUs, and Generating Timestamp Logs with RF from XML

Understanding the Relationship Between Linux Threads, Cores, and CPUs, and Generating Timestamp Logs with RF from XML

Understanding the Relationship Between Linux Sockets, Cores, Threads, and CPUs **CPU(s)**: Represents the total number of logical CPUs in the system. It is calculated by multiplying the number of physical CPU cores, the number of threads per core, and the number of physical CPUs in the system. For example, a system with 2 physical CPUs … Read more