Understanding DRAM Memory: A Five-Minute Guide to How Memory Works

Understanding DRAM Memory: A Five-Minute Guide to How Memory Works

Table of Contents 【CH.1】What is DRAM? Why is it important?【CH.2】Basic unit of DRAM: Capacitor, Transistor, and Storage Principle【CH.3】Column Address, Address Bus, and the Need for Address Multiplexing.【CH.4】RAS (Row Address Strobe), CAS (Column Address Strobe), WE (Write Enable).【CH.5】Step by Step, with Delay Explanation (RAS-to-CAS Delay, CAS Latency).【CH.6】Step by Step, explaining how data is written and refreshed.【CH.7】Why … Read more

Ascend NPU Processor Hardware Architecture and Key Technologies

Ascend NPU Processor Hardware Architecture and Key Technologies

With the rapid development of artificial intelligence technology, Deep Neural Networks (DNN) have become an indispensable computational model in various fields, especially in image recognition, speech processing, natural language processing (NLP), and intelligent driving. To effectively handle large-scale DNN computational tasks, traditional computing architectures (such as CPUs and GPUs) can no longer meet the growing … Read more

The ‘Data War’ of Multicore Chips: What is the Cache Coherence Problem?

The 'Data War' of Multicore Chips: What is the Cache Coherence Problem?

Hello everyone, welcome to my column. In previous articles, we explored the benefits of Thread-Level Parallelism (TLP) and the classifications of TLP architectures. Today, let’s learn about the cache coherence problems faced by shared memory architectures. Table of Contents 1. Shared Memory Architecture 2. Cache Coherence Problems Table of Content Mind Map 01Shared Memory ArchitectureShared … Read more