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On June 4, 2018, domestic ADAS company Maxieye Intelligent Driving Technology announced the launch of its second-generation pre-installed mass production front-view product IFVS-400, which is developed based on low-cost ASIC chips and employs deep learning algorithms, supporting L2/L3 level autonomous driving solutions.
The use of ASIC chips by ADAS companies is not common; most startups typically use FPGA solutions in some mass production projects due to factors such as flexibility, cost, and automotive-grade requirements.
Maxieye CEO Zhou Shengyan stated that while ASICs have a longer initial development cycle, FPGA or GPU+FPGA heterogeneous solutions were merely a “stopgap” for the market before 2017. By 2018, the cost and computational advantages of FPGAs have relatively diminished, with ASIC costs being about 20%-30% lower.
With automotive electronics giants like Qualcomm, TI, Renesas, and NXP starting to develop deep learning-based processor units around 2014, they generally chose the ASIC route. In the future, as the production and sales of ASICs increase, the advantages in price and cost will become more apparent.
The Long and Short of ASICs
ASIC (Application Specific Integrated Circuit) refers to integrated circuits designed for specific functions, such as dedicated audio and video processors, which have advantages like small size, low power consumption, high reliability, strong confidentiality, high computational performance, and high computational efficiency.
In the automotive industry, traditional applications of ASICs include control of the three electric systems, braking, acceleration, steering control, ABS, TSC, ESP, as well as various sensors and sensor interfaces, primarily supplied by traditional giants like NXP (Freescale), Renesas, TI, and ST.
ASICs are more about fully customized or semi-custom integrated circuits tailored to specific applications or user requirements, with relatively high development costs and a longer timeline from design to tape-out (generally over six months).
However, for end customers using the chips, they offer advantages such as shorter design and development cycles, lower design and manufacturing costs, advanced development tools, no need for testing of standard products, stable quality, and real-time online inspection.
The process of designing and producing an ASIC generally includes system design, detailed design, RTL-level coding, RTL-level simulation, using synthesis tools to generate netlists and SDF files for pre-simulation, layout and routing, post-simulation, sample production, and collaborative hardware-software debugging.
In contrast, for FPGAs, after synthesis and compilation, if there are no issues, testing can be performed directly on the FPGA substrate for system-level validation.
Comparatively, implementing with FPGAs can save two steps: one post-simulation and one sample production. Depending on the design and process manufacturers, these two steps typically require six weeks or longer. If mass production is needed, the first batch of ASIC chips would still require five weeks or more.
However, if there is an error in the sample, it would take at least six weeks or longer to rectify, so from a product time cost perspective, FPGAs have a significant advantage, allowing production to be at least three months faster than ASICs.
Of course, this difference also leads to another issue: if an ASIC has an error, the cost of modification is high, requiring a complete restart, which consumes more time and cost.
On the other hand, FPGAs can be upgraded simply by reprogramming without major changes, providing more flexibility during the launch of new products. Therefore, ASICs are generally used for technologies that are already mature and stable in the market.
Gate Arrays and Standard Cells
ASIC chips are primarily manufactured by semiconductor manufacturers using semi-custom methods, commonly using Gate Arrays and Standard Cells.Gate Arrays and Standard Cells have different internal structures and manufacturing technologies, resulting in differences in cost, production time, and efficiency.
Gate Arrays are a type of integrated circuit design technology programmed with masks, including CMOS Gate Arrays, Emitter Coupled Logic (ECL) Gate Arrays, BiCMOS Gate Arrays, and digital and analog compatible Gate Arrays. Semiconductor manufacturers pre-fabricate a regular array of logic gates or elements on the chip, processing it up to the interconnection photolithography step, resulting in a semi-finished chip known as a Gate Array substrate.
Then, manufacturers design the interconnection layout according to customer requirements and perform fabrication and photolithography processing, turning the chip into a dedicated integrated circuit that meets user requirements.
Gate Array substrates can be mass-produced, requiring only changes to the interconnection layout to adapt to various requirements. Typically, the programmed process layer is limited to the final interconnection (single or multiple wiring layers). The advantages of Gate Array design technology include short cycles, low costs, high success rates, and good reliability; however, it also has drawbacks such as insufficient design flexibility, low gate utilization, and higher power consumption.
Standard Cells are currently a widely used type of semi-custom chip.Semiconductor manufacturers pre-design unit circuits with certain logic functions (such as flip-flops, adders, counters, and RAM, etc.), and the layout and wiring of these unit circuits have been completed and rigorously tested to ensure logical functionality and good timing performance, then provided to designers in the form of a standard cell library.
ASIC designers can connect these pre-designed functional units together to achieve the required functionality, optimizing the layout and wiring on the chip as much as possible.
Unlike Gate Arrays, although these standard logic units are pre-designed, they are not pre-placed on the chip (as manufacturers do not know the designer’s design situation in advance, there is no universal way to determine the quantity and specific placement of various logic units). Therefore, standard cell design does not have the concept of a substrate. Each chip is temporarily produced based on the designer’s needs, and the most basic transistors within the chip are field-etched.
Thus, the production cycle of standard cells is longer than that of Gate Arrays. Since each layer of masks for standard cells is customized based on different user requirements, users cannot share development costs, making the trial production costs of standard cell ASICs higher than those of Gate Array ASICs.
The advantages of standard cell structures include small chip size, support for complex designs, low costs for mass production of single chips, and good user customization. For Gate Arrays, the substrate is pre-produced, and the chip size is fixed, with resources evenly distributed within the chip, many of which may not be fully utilized.
However, for standard cells, only the required standard cells will be placed on the chip, so the smaller the chip size, the more chips can be cut from each wafer, leading to lower costs per chip. This is the advantage of standard cell ASICs in large-scale production.
ASICs Stand on the Frontline
At the end of 2017, NIO chose the Mobileye EyeQ4 chip for its first mass-produced autonomous driving model, the ES8, which has a maximum computing speed of 25 trillion operations per second and a power consumption of 3W; this chip is an ASIC.
The EyeQ4 uses a set of industrial-grade quad-core MIPS processors operating at 1GHz to support multi-threaded technology for data control and management; multiple dedicated Vector Microcode Processors (VMP) are used to handle ADAS-related image processing tasks; a military-grade MIPS Warrior CPU is located in the secondary transmission management center to process general data inside and outside the chip.
In the same year, Musk revealed at an event that “Tesla is making its own chips,” clearly stating that “Jim is developing dedicated AI hardware,” which likely refers to ASIC chips.
Horizon also launched an ASIC artificial intelligence chip at the end of 2017, specifically for autonomous driving, produced by wafer foundry partner TSMC using advanced process technology. The NPU (Neural Processing Unit) can improve efficiency by 2-3 orders of magnitude (approximately 100-1000 times), featuring high performance, low power consumption, and low cost.
Domestic and foreign manufacturers are sporadically launching autonomous driving ASIC chips, while traditional automotive chip manufacturers have not rushed to announce their entry into this blue ocean.
Industry insiders have told GGAI Intelligent Automotive that the advantages of ASICs mainly lie in their application to mature and stable technologies that do not require constant upgrades, and that they need to have guaranteed usage volume to reflect cost and reliability advantages.
Under current technological conditions, ASIC chips for autonomous driving algorithms and control are still in the early stages, mainly due to the continuous updates and evolution of autonomous driving algorithms, which have not yet stabilized.
In the future applications of autonomous driving, there will be a greater emphasis on integration, with various fixed autonomous driving algorithms potentially embedded in the central processing system in the form of IP cores.
FPGA Supporters
To reaffirm its long-term investment in the automotive industry and its belief that FPGAs will play an important role in autonomous driving, Xilinx, one of the world’s largest FPGA suppliers, has been increasing its market cultivation efforts in recent years.
Although previously, FPGAs were more used in in-vehicle infotainment systems, Xilinx firmly believes that FPGAs are best suited for handling increasingly complex ADAS and autonomous driving.
In the ADAS field, Xilinx’s FPGAs have also been adopted by many startups to process data from various vehicle sensors (including cameras, millimeter-wave radars, etc.). FPGAs can leverage their DSP and parallel architecture to provide computational power that is extremely suitable for neural network acceleration.
Xilinx has previously claimed to hold the second-largest market share in automotive vision processing, second only to Mobileye, although there is a significant gap in market share between the two. However, Xilinx stated that it currently collaborates with several Tier 1 automotive suppliers, including Bosch, Magna, and Continental.
In the Chinese market, Xilinx is also exploring the market for ADAS startups.
Recently, AI startup Deep Insight Technology announced that it has completed the technical integration and commercial layout for the autonomous driving/advanced driver assistance field, achieving solution implementation and order conversion, with its product being the vehicle-mounted deep learning processing platform DPhiAutoTM based on Xilinx FPGAs.
At the beginning of this year at CES, another ADAS startup, MINIEYE, launched a pre-installed product X1 based on Xilinx FPGAs, which has already entered the supply chain of several automakers and Tier 1 suppliers, set to be equipped on mass production models this year.
MINIEYE stated that the choice of FPGA chips is due to their high computational performance, making them more suitable for deep learning; they are also automotive-grade chips that have been mass-produced, with more mature development, competitive costs, and significantly reduced power consumption.
Additionally, to address the limitations of single FPGAs, Xilinx has recently introduced another new product type following FPGAs: ACAP (Adaptive Compute Acceleration Platform). Xilinx states that it will far exceed the limits of FPGAs and will be able to stand alongside CPUs, GPUs, and FPGAs. The core of ACAP is a new generation FPGA architecture that combines distributed memory and hardware-programmable DSP modules, a multi-core SoC, and one or more software-programmable yet hardware-flexible computing engines, interconnected via an on-chip network (NoC).
Of course, it is still too early to draw conclusions about FPGA and ASIC; for major chip companies, this is a tough battle over cost, power consumption, and performance.
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