Red Semiconductor has announced the launch of a multifunctional intrinsic structured computing (VISC) architecture for RISC-V. VISC is an extension of RISC-V IP that accelerates complex algorithms and adds parallel processing to improveedge computing‘s AI operations.
Red Semiconductor’s CEOJames Lewis.
One of the strong value points of RISC-V is the potential for customization within the standard. Red Semiconductor leverages this to develop a licensable high-performance architecture. The VISC Instruction Set Architecture (ISA) adds edge AI, autonomy, and cryptographic capabilities to the open-source RISC-V. The code is optimized for FPGA and ASIC SoCs.
VISC is a vector processing engine built into RISC-V processor chips. It originated from the open-source Libre-SOC. Libra-SOC aims to bring complex algorithms (typically reserved for GPUs) to microcontrollers and CPU-based small devices. Red Semiconductor built VISC on Libra-SOC and the open-source CPU RISC-V architecture. The result is a CPU core that is compatible with RISC-V and has vector AI processing extensions.
Red Semiconductor claims that VISC outperforms other small systems/high computation demand processing devices while consuming less power. It enhances performance by using hardware components to deconstruct algorithms into blocks optimized for parallel processing.
It is claimed that the VISC RISC-V processor can improve the efficiency of algorithms typically used for artificial intelligence and machine learning, as well as other highly complex mathematical computations (such as cryptography and codecs), by up to 100 times. It relies on a single issue multiple execution architecture and memory-efficient 64 x 128 deep-byte accessible registers to reduce power consumption. The system breaks down algorithms into smaller parts that can be executed in parallel without the synchronization issues often encountered in parallel processing. By doing so, large computations can take less time and consume less power.
Developers have been adding CPU cores to FPGA and ASIC chips for some time, with Arm cores being one of the most popular. However, FPGA and ASIC developers relying on Arm are affected by the pace of Arm’s product releases. As RISC-V is open-source and adaptable, it has become a popular alternative for developers looking to accelerate the development of SoC products. With AI sweeping the globe, FPGA and ASIC device developers are eager for solutions, and this is where Red Semiconductor comes in.
Founded in 2021, Red Semiconductor is riding the wave of RISC-V and AI. Supported by the ChipStart UK incubator, the founders of Red Semiconductor saw an increasing demand from FPGA and ASIC developers for edge AI computing and more flexible AI options. VISC is their answer.
Red Semiconductor and Global Computing Challenges.
VISC brings accelerated AI capabilities to FPGA and ASICs that require RISC performance and flexibility. As an IP design, it can serve as a soft processor core added to FPGA configurations or as hard silicon in ASICs. As an enhancement to RISC-V, VISC brings optimized artificial intelligence and heavy mathematical computation capabilities to the fields of FPGA, ASIC, and SoC.
If 2023 is the year of cloud-based generative AI, then 2024 will be the year of edge AI. However, this technology requires remote devices to provide more power. Cars, smartphones, medical devices, industrial controls, and other field products need to process, interpret, make decisions, and take actions without spending time routing data to and from the cloud.
VISC provides developers with the option to add highly AI-optimized RISC-V to their edge devices while keeping power consumption and cost budgets conservative.
Source | Semiconductor Industry Observation (ID: icbank) compiled from allaboutcircuits
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