Embedded Communication Protocols
With the advent of the era of integration between communication and computing, digitization, broadband, and intelligence have become the future directions of communication development. Human society has increasingly high demands on telecommunication services, from quality to types of services. The access network, as an important component of the telecommunications network, connects local switches and users, serving as the capillary and bottleneck of the entire telecommunications network. It is key to achieving digitization, broadband, and service integration.
Embedded systems are specialized computer systems based on application-centered hardware design and application-oriented software product development. In embedded systems, the on-board communication interface refers to the communication pathways or buses used to connect various integrated circuits with other peripheral devices. The commonly used on-board communication interfaces will be explained one by one.
The I2C bus is a synchronous, bidirectional, half-duplex two-wire serial interface bus. Here, half-duplex means that at any given moment, communication can only occur in one direction.The I2C bus was first developed and marketed by Philips Semiconductor in the 1980s, with the initial design goal of providing a simple method for connecting microprocessor/microcontroller systems to peripheral chips of televisions.The I2C bus consists of two lines: the serial clock line SCL and the serial data line SDA. The SCL line is responsible for generating synchronous clock pulses, while the SDA line is responsible for transmitting serial data between devices.
The I2C bus is a shared bus system, allowing multiple I2C devices to be connected to the system. Devices connected to the I2C bus can act as either master devices or slave devices. The master device is responsible for controlling communication, initializing/terminating data transmission, sending data, and generating the required synchronous clock pulses. The slave device waits for commands from the master device and responds to received commands.Both master and slave devices can act as sending or receiving devices. Regardless of whether the master device is sending or receiving, the synchronous clock signal can only be generated by the master device. I2C supports the simultaneous presence of multiple master devices on the same bus.
Based on input buffers and open-drain transistors (or collector-open transistors), an I2C bus interface can be constructed. When the bus is idle, the open-drain transistor (or collector-open transistor) is in a floating state, and the output lines (SDA and SCL) are in a high-impedance state.
To ensure the bus operates normally, pull-up resistors should be used to pull both lines up to the supply voltage (for TTL series devices, +5V; for CMOS series devices, +3.3V). The typical value for pull-up resistors is 2.2K. Using pull-up resistors ensures that when the output lines on the bus are idle, they correspond to a high level.
By hard-wiring the device address lines to the required logic levels, the addresses of I2C devices can be assigned. In embedded devices, when designing embedded hardware, it is necessary to assign addresses to various I2C devices and complete the hardware connections. The sequence of operations for the system to communicate with I2C slave devices is as follows:
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The master device pulls the clock line (SCL) high to a high level.
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When the SCL line is at a high logic level (this is the start condition for data transmission), the master device pulls the data line (SDA) low to a low level.
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The master device sends the address of the slave device (which can be 7 or 10 bits wide) to the communication target address via the SDA line. The slave device will generate clock pulses on the SCL line to synchronize bit reception. It should be noted that the system always transmits the MSB (most significant bit) of the data first. The data on the bus is valid during the high level of the clock signal.
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As needed, the master device sends a read or write bit (a bit value of 1 means a read operation, while a bit value of 0 means a write operation).
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The master device waits for the slave device to send an acknowledgment bit. The address of the slave device is also sent to the bus simultaneously with the read/write operation command.For slave devices connected to the bus, the received address will be compared with the assigned address.
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If the slave device receives the command from the master device and the address is correct, the slave device sends an acknowledgment bit (value of 1) via the SDA line.
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After receiving the acknowledgment bit, if the operation command is to write data to the device, the master device sends 8 bits of data to the slave device via the SDA line. If the operation command is to read data from the device, the slave device will send data to the master device via the SDA line.
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For write operations, after the byte transmission is completed, the master device waits for the slave device to send an acknowledgment bit; for read operations, after the byte transmission is completed, the master device sends an acknowledgment bit to the slave device.
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When the clock line SCL is at a logic high level (indicating stop), the master device can terminate data transmission by pulling the SDA line high.
The I2C bus supports three different data rates: standard mode (data rate of 100kb/s, or 100kbps), fast mode (data rate of 400kb/s, or 400kbps), and high-speed mode (data rate of 3.4Mb/s, or 3.4Mbps). The first generation of I2C devices supported a data rate of only 100kbps, while the new generation of I2C devices can operate at data rates of up to 3.4Mbps.
The SPI bus is a synchronous, bidirectional, full-duplex four-wire serial interface bus, first proposed by Motorola. SPI is a system composed of “one master device + multiple slave devices”. It is important to note that as long as only one master device is active at any given time, multiple SPI master devices can exist in the system. To achieve communication, SPI has a total of four signal lines:
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Master Out Slave In (MOSI): The signal line that transmits data from the master device to the slave device, also known as Slave Input (SI/SDI).
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Master In Slave Out (MISO): The signal line that transmits data from the slave device to the master device, also known as Slave Output (SO/SDO).
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Serial Clock (SCLK): The signal line that transmits the clock signal.
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Slave Select (SS): The signal line used to select the slave device, active low.
The master device is responsible for generating the clock signal and selects the required slave device by pulling the corresponding slave select signal low. When not selected, all slave devices’ data output lines (MISO) are in a high-impedance state.
The serial data transmission on the SPI bus is user-configurable. SPI devices contain specific registers that can save the required configurations. The control register of the serial peripheral device is used to save various configuration parameters, such as master/slave selection, communication baud rate selection, clock signal control, etc. The status register is used to save the status of various communication conditions to achieve the required data transmission and reception.
The operation of SPI is based on shift registers; to achieve data transmission or reception, the master and slave devices contain dedicated shift registers. The length of the shift register depends on the specific device, usually an integer multiple of 8. During the process of data transmission from the master device to the slave device, the data in the master device’s shift register is shifted out from the MOSI pin, then input into the slave device’s shift register through the slave device’s MOSI pin.
Meanwhile, the data shifted out from the slave device’s shift register is input into the master device’s shift register through the MISO pin. In other words, the shift registers of the master and slave devices form a circular buffer. For specific types of devices, the first data bit sent can be determined by configuring the register (for instance, for the Motorola 68HC12 controller, the LSBF bit of the SPI control register needs to be configured) to decide whether the highest bit or the lowest bit is sent first.
Compared to the I2C bus, the SPI bus is more suitable for data stream transmission. However, the drawback of SPI is that it does not support a data acknowledgment mechanism.
Data transmission based on UART is an asynchronous form of serial data transmission. UART-based serial data transmission does not require the use of a clock signal to synchronize the transmission between the sender and receiver but relies on predefined configurations between the sending and receiving devices.
For both the sending and receiving devices, their serial communication configurations (baud rate, number of bits per unit, parity, number of start and stop bits, flow control) should be set to be exactly the same. By inserting specific bit sequences into the data stream, the start and end of communication can be indicated. When sending a byte of data, a start bit is added at the beginning of the bit stream, and an end bit is added at the end of the bit stream. The least significant bit of the data byte follows immediately after the start bit.
The start bit is used to inform the receiving device that: A data byte is about to arrive at the receiving end. The receiving device then selects its data receiving line according to the set baud rate. If the baud rate is x bits/second, then each bit has a time slot of 1/x seconds. The receiving device will accurately select the data receiving line at the midpoint of the available bit time slot.
If communication uses parity checking, the UART sending device will add a parity bit (value of 1 indicates there are an odd number of 1s in the transmitted bit stream; value of 0 indicates there are an even number of 1s). The UART receiving device calculates the parity result of the received data bits and compares it with the received parity bit.
The UART receiving device discards the start bit, end bit, and parity bit from the received bit stream and converts the received serial bit data into words (for instance, considering 8 bits corresponding to 1 byte, when receiving 8 bits, the first received data bit is LSB, and the last received data bit is MSB). To achieve correct communication, the data transmission line of the sending device should be connected to the data receiving line of the receiving device.
In addition to serial data transmission capabilities, UART can also provide hardware handshaking signal support for controlling serial data flow.Many semiconductor manufacturers provide corresponding UART chips. The 8250 UART produced by National Semiconductor is a standard UART used in early designs of IBM PCs.
Today, most microprocessors/controllers are integrated with UART functionality and provide built-in instruction support for serial data transmission and reception.
The 1-Wire interface is an asynchronous half-duplex communication protocol developed by Maxim Dallas Semiconductor, also known as the Dallas 1-Wire® protocol. In this protocol, communication is achieved using a single signal line DQ according to the master-slave communication model.An important feature of the 1-Wire bus is that it allows power to be transmitted over the signal line. I2C slave devices use internal capacitors (typically 800 pF) on the signal line to drive the devices. The 1-Wire interface supports the connection of a single master device and one or more slave devices on the bus.
Each 1-Wire device has a globally unique 64-bit identification code stored within the device. In the case of multiple slave devices connected to the 1-Wire bus, the unique identification code can be interpreted to address the individual devices present on the bus. The identification code consists of three parts: an 8-bit type code, a 48-bit serial number, and an 8-bit CRC check result for the first 56 bits of data. The specific process for communicating with 1-Wire slave devices is as follows:
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The master device sends a reset pulse to the 1-Wire bus.
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The slave devices on the bus respond with an acknowledgment pulse.
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The master device sends a ROM command (network addressing command, with the parameter being the 64-bit address of the device) to address the slave device that needs to initiate communication.
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The master device sends read/write commands to read/write operations on the internal memory or registers of the slave device.
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The master device reads data from the slave device or writes data to the slave device.
All communication on the 1-Wire bus is initiated by the master device. The minimum interval for communication is a time slot of 60 microseconds. The reset pulse occupies 8 time slots. At the beginning of communication, the master device pulls the 1-Wire bus low and holds it for 8 time slots (480 μs) to issue a reset pulse. If there are slave devices on the bus that are ready for communication, they will respond to the master device with an acknowledgment pulse; that is, the slave device will pull the 1-Wire bus low for 1 time slot (60 μs).
To write a bit value of 1 on the 1-Wire bus, the master device must pull the bus low for a duration of 1 to 15 μs and then release the bus for the remainder of the time slot. To write a bit value of 0 on the bus, the master device must pull the bus low for at least 1 time slot (60 μs) and at most 2 time slots (120 μs). To read a bit value from the slave device, the master device must pull the bus low and hold it for 1 to 15 μs.
To respond to the master device’s read data request, if the slave device wants to send a bit value of 1, it only needs to release the bus for the remainder of the time slot; if it wants to send a bit value of 0, it needs to pull the bus low for the remainder of the time slot.
The on-board parallel interface is typically used for communication between the system and peripheral devices, where the peripheral devices are memory-mapped to the system’s main control unit. As long as the main processor/controller of the embedded system has a parallel bus, devices that support the parallel bus can be directly connected to this bus system.The peripheral devices have control signal interfaces to control data communication on the parallel bus. Here, the control signals for communication include read/write signals and device select signals.Generally, peripheral devices have a device select line; only when the main processor selects this line is the device valid. The direction of data transfer can be from the main control unit to the peripheral device or from the peripheral device to the main control unit; this is controlled through the read and write control signal lines. Only the main processor can control the read control signal and write control signal.
Generally, peripheral devices are memory-mapped to the main processor, allowing access to the allocated address range. At this time, the device needs to use address decoding circuits to produce chip select signals. When the address selected by the processor is within the designated range of the device, the decoding circuit triggers the chip select line, activating the device. The processor can then enable the corresponding control lines (RD or read and WD or write) to read data from the device or write data to the device.
To achieve parallel communication, the system needs to strictly follow timing specifications. As mentioned earlier, parallel communication is initiated by the main processor. If a peripheral device wants to initialize communication, it can issue an interrupt to the processor to inform it of the relevant information.
To achieve this functionality, the interrupt line of the device needs to be connected to the interrupt line of the processor, and the main processor needs to trigger the corresponding interrupt. It should be noted that the width of the data bus of the main processor determines the width of the parallel interface, which can be 4, 8, 16, 32, 64 bits, etc. The bus width supported by the device should be identical to that of the main processor.
Source:Electronic Product World
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