I3C: The Next Generation Serial Communication Technology
The Electronic Enthusiast Network reports (by Li Ningyuan) that the I2C bus, a well-known simple, bidirectional two-wire synchronous serial bus technology developed by Philips, requires only two wires to transmit information between devices connected to the bus. It has been widely used to connect various sensors, LCD screens, and memory.Previously, the impression of I2C was that it combined the advantages of SPI and UART, being both lightweight and simple, while also being cost-effective. I2C allows for fast and reliable data transmission between controllers and peripheral devices, and it can support interconnecting multiple devices for various data transmissions.However, with the changing demands of application scenarios, the long-standing shortcomings of I2C have been fully exposed, prompting an upgrade in serial bus technology.
I2C Decline: Upgrading from I2C to I3C
Over the past few decades, the widespread use of I2C has demonstrated its solid position in hardware communication, with its lightweight, simplicity, and low cost being widely recognized. However, while I2C is a primary interface choice for embedded devices, relatively easy to implement and widely adopted over the years, it lacks certain important features and has limitations, presenting unavoidable drawbacks. This is especially true in deeply embedded applications, which severely impact the design of compact systems. These drawbacks include limited speed, limited transmission distance, and relatively high power consumption.The communication distance of the I2C protocol is relatively short and is easily affected by factors such as cable length and signal attenuation, so I2C is generally only used for close-range device connections. Transmission speed is not an advantage of I2C; previously, due to limited transmission speeds, there have been many cases of SPI replacing I2C, but SPI itself has a broader range of applications and ultimately did not replace I2C.As smartphones, wearable devices, IoT devices, automotive systems, and server environments become increasingly advanced and complex, there is a need for more streamlined, high-performance, scalable, and cost-effective communication interfaces to control and transmit data at high speeds while also requiring energy-saving and space-saving designs.As the amount of bus data begins to expand, I2C has reached the bottleneck of the technology. To overcome the performance deficiencies of I2C under new demands, the MIPI Alliance sensor interface working group initiated an upgrade based on I2C requirements early on.In 2016, the MIPI Alliance officially released the first I3C specification v1.0. The initial version of I3C aimed to provide the functional baseline needed to integrate different types of sensors, including high clock speeds, invented interrupts or connections, high data rate modes, and timing control.I3C, as an upgraded version of I2C, formally began to take over the baton of serial bus technology from I2C. Defined as a smart multifunction interface, I3C integrates and unifies the key attributes of I2C and SPI, while improving the functionality and performance of each approach through a comprehensive, scalable interface and architecture. The specification also anticipates the sensor interface architecture required for future mobile, mobile impact, and embedded systems industries.Overall, I3C, which uses complementary metal-oxide-semiconductor (CMOS) I/O to achieve serial communication, employs a two-wire system to minimize the number of pins and signal paths between components, which is crucial for space-constrained IoT and wearable devices. This interface also supports higher bandwidth operating modes at extremely low power levels, facilitating simpler and more flexible designs.
The Functional Evolution of I3C
After the release of I3C v1.0, multiple versions have been updated and iterated. In 2018, I3C basic v1.0 was released, mainly providing a function-limited available version for non-MIPI members, and added basic functionalities related to sensor integration and DDR5.By the v1.1 version in 2019, more features were introduced, including HDR-BT Mode, Group Addressing, Multi-Lane for Speed, and Target Reset. The introduction of these features has allowed I3C to further leverage its advantages in memory management, communication debugging, and power management.As of the latest version v1.1.1, relevant features have been further optimized and enhanced, distinguishing between MIPI member versions and basic versions. Features missing in the basic version have also been supplemented, such as the addition of a Reset mechanism for the Slave, which enhances the protocol’s fault recovery capability using methods to exit HDR mode.Compared to I2C, the improvement in transmission speed of I3C is the most obvious. The I2C protocol specifies three speeds (bps): 100K, 400K, and 3.4M. In contrast, I3C supports communication speeds ranging from 12.5 Mbps to nearly 37.5 Mbps. This is something that traditional I2C, SPI, and UART lack, and it directly addresses the transmission demands of expanding data volumes.The upgrade in transmission speed has not led to power consumption issues. The two wires of traditional I2C, SCL and SDA, need to be connected to pull-up resistors, and the presence of pull-up resistors results in relatively high power consumption for I2C. In contrast, I3C employs push-pull for SCL throughout, and SDA operates in push-pull mode most of the time, significantly reducing power consumption.In terms of energy consumption (per data bit), I2C consumes nearly 4 in SDR mode, while I3C does not exceed 1.5. The significant reduction in power consumption allows I3C to more easily adapt to various transmission applications. Additionally, I3C features a working mode that reduces speed to ensure accuracy, further lowering energy consumption.Another pain point is transmission distance. The theoretical transmission distance of I2C can reach 10 meters, but in actual applications, it rarely achieves this distance. I2C is highly susceptible to interference and is basically only suitable for communication between board-level devices, often struggling with mid-range distances.According to the protocol specifications, I3C can theoretically achieve a communication distance of up to 100 meters. Although it is unlikely to challenge this theoretical transmission distance in practice, mid-range communication transmission is not a problem, and the overall load capacity of I3C has improved its anti-interference capability, making it less susceptible to interference compared to I2C.
Highlighting I3C Features in End Applications
The upgrade from I2C to I3C is currently progressing steadily. I3C retains backward compatibility with I2C, gradually upgrading and replacing I2C in various applications. Market shifts take time, but some applications have already begun to leverage unique advantages with I3C.The most typical examples are smartphones and IoT devices, which contain many combinations of I2C and SPI devices. I2C requires many additional slave connections to the device’s SoC, increasing the number of GPIOs to add SoC package pins and PCB layer counts, raising system costs, and increasing overall power consumption. The introduction of the I3C mechanism reduces both system costs and significantly simplifies design complexity.I3C is also increasingly being applied in servers and wireless base stations. This is thanks to the introduction of I3C’s hot-join feature, which allows certain devices on the bus to be turned on and off during operation, enabling a “segmented power supply” design. In servers or wireless base stations, many systems cannot be powered down, necessitating designs with hot-swappable functionality, making this feature of I3C very important for these applications.DDR5, a core application of MIPI I3C, will undoubtedly upgrade to I3C for the next generation of high-performance data systems. DDR5 can significantly improve memory bandwidth by using MIPI I3C, addressing design challenges in next-generation data systems. The high performance of I3C, exceeding 30 Mbps (single-channel mode) and 100 Mbps (four-channel mode), is undoubtedly beneficial for optimizing DDR5.
In Conclusion
I3C, as a scalable, practical, and controllable bus interface upgraded from I2C, facilitates the connection of peripheral devices to application processors more conveniently. Its simplicity, high integration, and cost efficiency are very evident, providing innovative design ideas for smartphones, wearable devices, automotive systems, and any mobile products.As this technology gradually replaces I2C, from smartphones and wearable devices to PCs and large automotive systems and computing centers, it is bound to become the mainstream serial bus technology in various applications.
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