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At the recent 2025 TSMC OIP Ecosystem Forum, the semiconductor I/O field has undergone tremendous changes, which is evident.
Over the past 25 years, the semiconductor I/O field has experienced profound transformations, evolving from simple general-purpose input/output (GPIO) units at the 180nm process node to today’s highly complex libraries at advanced 16nm and 22nm processes that support multiple protocols and are feature-rich. As experts elaborated in their presentations, modern I/O design no longer focuses solely on basic functionality but places greater emphasis on adaptability, optimization, and performance tailored to specific markets.
Historically, each process node required only a basic I/O library to meet demands, providing various variants of classic GPIO (push-pull LVCMOS) or open-drain I/O (ODIO) that supported protocols like I2C or SMBus. These were sufficient to meet the application needs of telecommunications and consumer electronics in the early 21st century. Today, the explosive growth in areas such as mobile computing, the Internet of Things (IoT), edge artificial intelligence, in-vehicle infotainment systems, and autonomous driving systems has raised the bar for flexibility. Now, a single ASIC chip can serve both automotive (requiring CAN) and cellular (requiring I3C) markets without dedicated pins. This convergence has given rise to GPODIO, a hybrid I/O that can operate in both CMOS and open-drain modes, supporting LVCMOS, SPI, I3C, JTAG, and fail-safe open-drain standards.
GPODIO is a prime example of multi-protocol I/O and a cornerstone of modern design. It features configurable output drivers that can switch between high-speed GPIO (Tfall < 5ns, Zout 33–120 Ω) and slow transition open-drain modes (Tfall 20–1000ns, IOL 3–20mA). Input Mode Control (IMC) supports various VIH/VIL/hysteresis thresholds, while fail-safe operation ensures reliability even with push-pull drivers and on-chip termination. The voltage support range has also been expanded: modern GPIO can handle VDDIO from 1.2V to 3.3V, core power as low as 0.65V, and external ODIO voltages up to 5V—all integrated into a single unit.
Even more advanced is the “super” I/O, which is a macro unit containing two single-ended or one differential pair, supporting over 20 standards, including LVDS, MIPI, HSTL/SSTL with on-die termination (ODT), and POD. These are crucial for high-performance computing (HPC) and 5G infrastructure.
Another major trend is the variation of I/O libraries. At the 22nm process node, a GPIO design may derive five libraries—PM22 (ultra-low power IoT, leakage current 0.14nA), MM22 (balanced mobile applications), OG22 (automotive grade, 8kV HBM), and EG22/TG22 (high-performance computing, using interleaved packaging for increased density). Each library is optimized for speed, leakage current, electrostatic discharge (2kV to 16kV HBM, 6A to 16A CDM), and interface support (SPI, RGMII, eMMC). Today, foundries offer multiple libraries for each node, differentiated by metal layers, voltage, and market positioning. Product architects must choose the appropriate library based on application goals—for example, using a low-power IoT library for high-performance computing would degrade performance.
Analog and RF I/O technologies are also maturing. In the past, designers needed to build custom pads, but today’s libraries include pre-characterized units: low-capacitance RF pads (<75fF, >8kV HBM), matched LVDS/HDMI pairs, and high-voltage analog I/O up to 20V. This reduces design risk and shortens time to market.
The emerging 2.5D/3D packaging and chip-to-chip interfaces introduce ultra-low power, high-density I/O (e.g., 4Gbps at 16nm process, DC current <0.1nA, 10×20µm size), which is critical for multi-chip AI and memory stacking.
Verification complexity has risen sharply. Traditional GPIO required about 135 PVT corner points; modern multi-voltage, multi-mode GPIO requires over 12,000 corner points, including zero volts and power-down modes. Accurate .LIB modeling has now become a significant engineering challenge.
In summary, I/O design has transformed from a single, one-size-fits-all library to a complex ecosystem composed of optimized, configurable, and market-customized solutions. The era of defaulting to “basic” foundry libraries is long gone. To succeed in 2025, a deep understanding of application requirements, careful library selection, and rigorous verification are essential—ensuring that performance, power consumption, reliability, and cost meet the diverse and demanding needs of end markets.
(Source: Content compiled from semiwiki)
*Disclaimer: This article is original by the author. The content reflects the author’s personal views, and Semiconductor Industry Observer reproduces it solely to convey a different perspective, not representing Semiconductor Industry Observer’s endorsement or support of this view. If there are any objections, please contact Semiconductor Industry Observer.
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