This article is reprinted from the Zhihu community by the authorTian Tian’s Little Tiger’s Column, and the reprinted article is for learning and research purposes only.
Introduction
MIPI: The full name is Mobile Industry Processor Interface.MIPI is an open standard initiated by the MIPI Alliance for mobile application processors. MIPI can be divided into two main parts: the physical layer and the logical layer.MIPI is categorized into three types based on the physical layer (Physical Standard): D-PHY, C-PHY, and M-PHY.D-PHY MIPI OverviewThe logical layer of D-PHY is mainly aimed at applications such as cameras (CSI) and displays (DSI). The ‘D’ in D-PHY represents the Roman numeral 500, indicating that the initial version of D-PHY supports up to 500 Mbits/s. D-PHY uses differential signaling (not entirely differential, as LP is single-ended), with each lane consisting of two signal lines, P and N. The clock lane is essential, and the number of data lanes can be selected based on the data transmission throughput, with at least one data lane required.C-PHY MIPI OverviewC-PHY is similar to D-PHY, with its logical layer also primarily aimed at applications such as cameras (CSI) and displays (DSI). The ‘C’ in C-PHY refers to Channel-limited. C-PHY has a total of three lanes, each using three signal lines that are differentially paired. C-PHY does not have a separate clock; the clock signal is included in the communication timing.M-PHY MIPI OverviewM-PHY supports all chip-to-chip applications, as well as high-performance camera and memory applications. The chip-to-chip application protocols supported by M-PHY include DigRF, LLI, and CSI-3 for high-performance camera applications. M-PHY uses an embedded clock and is currently rarely used, being quite advanced.
D-PHY Electrical Characteristics Overview
D-PHY includes several electrical functions: High-Speed Transmission (HS-TX), High-Speed Reception (HS-RX), Low-Power Transmission (LP-TX), Low-Power Reception (LP-RX), and Low-Power Contention Detection (LP-CD). The PHY does not need to include all electrical functions; we configure its electrical functions based on requirements. However, any physical layer’s electrical characteristics must meet these electrical specifications. The following diagram shows the comprehensive electrical characteristics.During use, D-PHY, like other buses, has Master and Slave distinctions. For example, when using SoC to drive an LCD with D-PHY MIPI signals, the SoC is the Master, and the LCD is the Slave.The clock signal is a unidirectional signal, provided only from Master to Slave, and remains constant.Data signals can be unidirectional or half-duplex, meaning they can be transmitted in reverse. The essence of reverse transmission is actually reading data from the Slave by the Master. In this half-duplex bidirectional signal data transfer, the bandwidth during reverse transmission (Slave to Master) is only one-fourth of that during forward transmission (Master to Slave).
Pin Connection Method
Typically, connections are made as follows.
Lane Signal Amplitude and Definition
D-PHY Lane modes are divided into two types: High-Speed and Low-Power, with different signal amplitudes during transmission.High-Speed, also known as Burst Mode, is used for high-speed data transmission, specifically for image data transmission. In this mode, the throughput can reach 2500 Mbps, or 2.5 Gbps per lane.Low-Power mode is used for control information, such as sending commands, with a maximum rate of 10 Mbps.
As shown in the figure, HS represents High-Speed. In HS mode, differential signal transmission occurs, with signal levels between 100 mV and 300 mV (200 mV swing). In LP mode, the two lines on the Lane are independent signals, not having differential meaning, and are single-ended signal transmissions, with signal levels between 0 and 1.2 V (1.2 V swing).From the figure, it can be seen that the maximum swing of the HS differential transmission signal is less than the low voltage threshold of LP, so the LP receiving clock receives a low HS signal.Whether in HS mode or LP mode, LSB first and MSB last transmission is used.
Lane Modes
According to the spec, we know:Data Lane has High-Speed mode and Low-Power mode. Low-Power mode is further divided into Control Mode and Escape Mode, with Escape Mode further divided into Trigger, Ultra Low Power State, and Low-Power Data Transmission.Clock Lane has High-Speed mode and Low-Power mode, with Low-Power mode having Ultra Low-Power.See the detailed block diagram below.
Having understood the various modes above, how does MIPI D-PHY enter these modes? And how does it inform the other end that it has entered these modes?State CodeMIPI D-PHY defines state transitions through State Codes.
HS-0: Indicates that in High-Speed mode, the data on the Dp line is 0; since High-Speed is a differential signal, the Dn line is 1.HS-1: Indicates that in High-Speed mode, the data on the Dp line is 1; since High-Speed is a differential signal, the Dn line is 0.As mentioned earlier, in Low-Power mode, the two lines of the Lane are independent and do not represent differential signals, so there are four possible expressions for the two lines:LP-00: Indicates that in Low-Power mode, the data on the Dp line is 0, and the data on the Dn line is 0.LP-01: Indicates that in Low-Power mode, the data on the Dp line is 0, and the data on the Dn line is 1.LP-10: Indicates that in Low-Power mode, the data on the Dp line is 1, and the data on the Dn line is 0.LP-11: Indicates that in Low-Power mode, the data on the Dp line is 1, and the data on the Dn line is 1.D-PHY Data LaneHigh-Speed Data Lane TransmissionUnder normal circumstances, the Data Lane is either in Low-Power Mode or in High-Speed mode. How does it enter High-Speed?The MIPI D-PHY specifies that a Data Lane enters High-Speed by sending a Start-Of-Transmission Sequence, or SOT signal, which consists of:
That is, the sequence is set to LP-11, LP-01, LP-00, HS-0, send HS Sync 00011101 sequence, and then send data.After initiating High-Speed Transmission, how does one stop? MIPI defines something corresponding to SOT called End-of-Transmission, or EOT. Compared to the start of transmission, the process of stopping is relatively simple, as follows:
In simple terms, when preparing to stop, send LP-11,Thus, the entire timing diagram for starting and stopping high-speed transmission is as follows.
At the sender, it begins to enter Stop (LP-11), then pulls LP-01, LP-00, HS-0, sends the Sync field (HS-00011101), and then continuously sends differential data until the data transmission is complete (if completed), exits High-Speed mode, and re-enters Stop State; the Stop State is crucial, as it ultimately enters Stop mode, which can be understood as PHY being in standby;Bidirectional Data Lane TurnaroundPreviously, it was mentioned that the Data Lane is bidirectional, but only the unidirectional transmission part was seen. Here is the bidirectional transmission, referred to as Turnaround, which is completed in Control Mode. The specific process is as follows.Note that even during Turnaround, the roles of Master and Slave remain unchanged.
That is, LP-11, LP-10, LP-00, LP-10, LP-00, Wait ACK (receive LP-00), receive LP-10, receive LP-11.The timing is as follows:
Data Lane Escape ModeRemember when we discussed High-Speed and Low-Power? Low-Power is further divided into Control Mode and Escape Mode; here we will expand on Escape Mode.Note: The Escape mode here refers to the Data Lane, not the Clock Lane.Escape Mode is a type of Low-Power, and several subtypes are defined for Escape Mode. Based on previous introductions, we will expand: 1) Low-Power Data Transmission, abbreviated as LPDT, meaning data transmission in LP mode; 2) Ultra-Low Power State, abbreviated as ULPS, ultra-low power state; 3) Trigger, currently only one Trigger exists, which is Reset, used to trigger a Reset; they all reserve some content to accommodate future standard upgrades.Entering Escape ModeAs mentioned earlier, to enter Escape mode, a process called Escape mode Entry is required.This process is: LP-11, LP-10, LP-00, LP-01, LP-00.Unlike before, Escape mode defines some triggers and modes, so after executing a series of LPxx, which mode do you want to enter, or what do you want to trigger?Thus, an Entry Command is defined.In other words, to truly enter a sub-mode of Escape or trigger something, the following process is required:LP-11, LP-10, LP-00, LP-01, LP-00, [Entry Command]The Entry Command is encoded as:
Those Unknown and Undefined are reserved for future use;For example, taking Trigger Reset as an example, its timing is as follows:
Low-Power Data TransmissionIf the Entry Command specified for Low-Power Data Transmission when entering Escape mode, it will enter this LPDT mode. In this mode, data can be transmitted at low speed, and the Lane can pause transmission.
As seen, after transmitting the First Data Byte, there is a pause before the Second Data Byte.Ultra-Low Power StateIf the Entry Command specified for Ultra-Low Power State (ULPS) when entering Escape mode, this Lane will enter ULPS.D-PHY Clock LaneThe Clock Lane is somewhat different from the Data Lane; although both can be abstracted as single-ended high-speed differential signals, the Clock Lane does not have an Escape mode, but it does have a ULPS mode.Clock Lane High-Speed And Low-PowerHere we focus on the timing of the Clock Lane and Data Lane when entering and exiting Low-Power:
It can be seen that when the Data Lane enters Stop State, after Tclk-post, the Clock Lane enters HS-0 state, and then maintains HS-0 for a duration of Tclk-trail before entering LP-11 state.However, when data needs to be sent, the Clock Lane first enters LP-11, then enters LP-01 and stays for Tlpx, enters LP-00 and maintains for some time Tclk-prepare, maintains HS-0 for Tclk-zero, and then the Clock Lane can operate normally. After Tclk-pre, the Data Lane can operate.The entire process is as follows:
Clock Lane Enters Ultra-Low Power StateAlthough no Escape mode is defined for the Clock Lane, it defines an Ultra-Low Power State, and the way to enter the Ultra-Low Power State for the Clock Lane is: LP-11, LP-10, LP-00.Contention DetectionUnder normal circumstances, at both ends of the connection, only one side can drive the signal on the line within a given time. If one end fails, for example, if both ends attempt to drive the same Lane simultaneously, or if neither end drives this Lane, D-PHY refers to this situation as “contention”.LP Lanes with bidirectional communication must have Contention Detection capability and monitor the following conflicts:1. Both modules simultaneously drive a line in the reverse direction;2. One end of the module drives a line as LP-high while the other end drives this line as HS-low;The first situation can be monitored by the combination of LP-CD and LP-RX;The second situation should be monitored by LP-RX;The monitoring principle can be referenced in the Spec.
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