Recently, while debugging an FPGA for video capture and playback, I utilized the MIPI CSI-2 TX Subsystem (2.2) IP. Debugging this board was quite challenging, and I encountered numerous pitfalls, especially since it was my first time working with video interfaces and I was unable to identify the issues. I will document the problems encountered during the debugging process and share them with everyone.The FPGA model used is xc7vx690tffg1157. The circuit has implemented 4 channels of MIPI, with MIPI1 on bank 35, MIPI2 on bank 34, MIPI3 on bank 34, and MIPI4 on bank 36. This FPGA model has a total of 32 BUFGs, and the program uses 4 DDRs, which occupy 3 BUFGs, along with GTH ports that occupy 16 BUFGs, and PCIe, which occupies 5 BUFGs. Additionally, a clock core is used, occupying 7 BUFGs. Each MIPI channel occupies 5 BUFGs, which means the resources are over-utilized. I had to make compromises by manually changing the 8 GTH TX channel BUFGs to BUFH, as there were no other options available. Although the clock IP could be modified, it has a high clock fanout, so it must use BUFGs, and I cannot change that. Other areas are also IP cores that do not provide users with the option to select BUFG types, and although I wanted to change them, I did not know how. The only solution was to cascade the 4 MIPI channels, allowing 3 of the MIPI channels to borrow clock resources from the main MIPI. However, while using cascading, I encountered a significant issue. I initially thought it was my fault and was close to a breakdown. The MIPI uses a BUFR, which is called a regional clock. This clock can only drive the clock of its own region. To use cascading, the MIPI must be in the same region as the main MIPI. However, among these 4 MIPI channels, only MIPI2 and MIPI3 are in the same bank area, allowing them to be cascaded. The other two MIPI channels must be used separately and cannot be cascaded. This issue must be considered when designing the schematic.