Simple Digital Clock Design Based on FPGA: VHDL Code and Quartus Simulation

Name: Simple Digital Clock Design Based on FPGA: VHDL Code and Quartus Simulation

Software: Quartus

Language: VHDL

Code Function:

Simple digital clock design

1. Design a base-24 counter, which can adjust the count value using buttons.

2. Design a base-60 counter, which can adjust the count value using buttons.

3. Design a display module.

4. Combine the above modules to create a digital clock that displays hours, minutes, and seconds, which can be set and shown on a seven-segment display.

1. Project Files

2. Program Files

Block Diagram

3. Program Compilation

4. RTL Diagram

5. Simulation Diagram

Overall Simulation Diagram

Base-60 Module Simulation Diagram

Base-24 Module Simulation Diagram

Display Module Simulation

Partial Code Display:

LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;
--Hour Module--Base-24
ENTITY wy_counter_24 IS
   PORT (
      clk      : IN STD_LOGIC;
      set_key  : IN STD_LOGIC;--Set Time
      cnt_ten  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--Count Value Tens
      cnt_one  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)--Count Value Units
   );
END wy_counter_24;
ARCHITECTURE behave OF wy_counter_24 IS
   SIGNAL clk_cnt      :  STD_LOGIC:='0';
   SIGNAL cnt_ten_buf : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";--Count Value Tens
   SIGNAL cnt_one_buf : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";--Count Value Units
BEGIN
   --Output
   cnt_ten <= cnt_ten_buf;
   cnt_one <= cnt_one_buf;
clk_cnt <= clk OR set_key;--Set Time and Clock OR operation, i.e., setting time can also control time
   
   PROCESS (clk_cnt)
begin
IF (clk_cnt'EVENT AND clk_cnt = '1') THEN--Normal Timing
         IF (cnt_ten_buf = "0010" AND cnt_one_buf = "0011") THEN--After 23 hours, change to 00
            cnt_ten_buf <= "0000";
            cnt_one_buf <= "0000";
         ELSIF (cnt_ten_buf = "0000" AND cnt_one_buf = "1001") THEN--09 changes to 10
            cnt_ten_buf <= "0001";
            cnt_one_buf <= "0000";
         ELSIF (cnt_ten_buf = "0001" AND cnt_one_buf = "1001") THEN--19 changes to 20
            cnt_ten_buf <= "0010";
            cnt_one_buf <= "0000";
         ELSE--Units accumulate
            cnt_ten_buf <= cnt_ten_buf;
            cnt_one_buf <= cnt_one_buf + "0001";
         END IF;
      END IF;
   END PROCESS;
   
   
END behave;