Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation

Name: Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation

Software: Quartus

Language: Verilog

Code Function:

Simple equal precision frequency counter design

Requirements

Measured Signal: TTL Square Wave

A. Frequency Measurement Range: 100Hz ~ MHz

B. Measurement Error: ≤0.1% (full scale);

C. Clock Frequency: 50kHz

D. Pre-gate Time: 0.1s

E. System Clock Frequency: 50MHz

F. Frequency Calculation: Retain 1 decimal place

G. The top-level design uses graphical input, and each module can be designed using functional modules or HDL languages.

1. Project Files

2. Program Files

DDS IP Core

3. Program Compilation

4. Testbench

5. Simulation Diagram

Partial Code Display:

// Frequency Divider Circuit Module
module clk_div(
input clk_50M,// 50MHz
output reg clk_50K// 50K output
);
reg [15:0] cnt=16'd0;
always@(posedge clk_50M)
if(cnt>=16'd10)// Count to 1000, reduce to 10 for simulation
cnt<=16'd0;
else
cnt<=cnt+1;
always@(posedge clk_50M)
if(cnt>=16'd5)
clk_50K<=1;// Divide by 50K
else
clk_50K<=0;
endmodule

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