Series Four: Embedded Microprocessors (MPU) in Software System Architecture

1. What is an Embedded Microprocessor?

The embedded MPU has evolved from the CPU of general-purpose computers, but has been functionally trimmed and optimized for embedded applications. It typically retains hardware modules closely related to the application (such as arithmetic units, controllers, and registers), removing redundant functions to reduce power consumption and cost.

Embedded Microprocessor (MPU) is a processing core designed specifically for embedded systems, capable of computation, control, and interface management, and typically lacks on-chip memory and peripheral controllers, requiring external modules for operation.

It serves as the brain of embedded systems, differing from microcontrollers (MCUs) in that MPUs are more oriented towards high-performance, complex system processing.

Core Features:

High Performance: Typically 32-bit or 64-bit processors (e.g., ARM Cortex-A series, PowerPC, MIPS).
Low Power Consumption: Extends device battery life through power management techniques (e.g., sleep modes, dynamic frequency scaling).
High Reliability: Suitable for harsh environments such as industrial and automotive applications, designed for interference resistance and stability.
Compact Size, Low Cost: Higher integration compared to industrial control computers, suitable for mass production.
Scalability: Connects memory and peripherals through external interfaces (e.g., SPI, I2C, USB), allowing flexible function expansion.

2. Core Functions

Memory Management:
Internally integrated high-speed cache, external support for RAM/ROM expansion.
Supports virtual memory management and memory protection mechanisms (e.g., MMU).
Clock and Timing:
Precise clock signal controls instruction execution cycles, providing timer interrupt functions (e.g., periodic task scheduling).
Peripheral Interfaces:
Integrates various communication interfaces (UART, SPI, I2C, CAN, Ethernet), supporting interaction with sensors, displays, and other peripherals.
Interrupt Handling:
Supports multi-level interrupt priorities, quickly responding to external events (e.g., key inputs, sensor triggers).
Power Management:
Dynamic voltage frequency scaling (DVFS), various low-power modes (sleep, standby), suitable for battery-powered scenarios.

3. Comparison with MCU (Key Dimensions)

Comparison Dimension	MCU (Microcontroller)	MPU (Microprocessor)
Integration Level	High: ROM, RAM, peripheral controllers integrated on-chip	Low: only the core processor is integrated
Performance	Lower, suitable for simple control	High, suitable for complex systems and multitasking
Operating System	Usually none or uses RTOS	Typically runs embedded Linux, Android, etc.
Storage Method	On-chip Flash/RAM	External DDR, eMMC, SPI Flash
Interface Richness	General: UART, SPI, I2C	Rich: USB, PCIe, Ethernet, HDMI, MIPI, etc.
Power Consumption	Ultra-low power, suitable for battery-powered devices	Relatively high, requires power management optimization
Cost	Low cost, suitable for mass production	Higher (requires peripheral circuits)
Application Scenarios	Home appliances, sensors, simple terminal control	Gateways, edge AI devices, multimedia playback, industrial control systems, etc.

4. Structure of Embedded Microprocessors

graph TD  
CU[Control Unit]  
ALU[Arithmetic Logic Unit]  
REG[Registers]  
MMU[Memory Management Unit]  
INT[Interrupt Controller]  
BUS[Internal Bus]  
CU --> BUS  
ALU --> BUS  
REG --> BUS  
MMU --> BUS  
INT --> BUS

Additional modules (may also be integrated in different processors): Floating Point Unit (FPU), Vector Processor, Encryption/Decryption Unit, NPU, etc.

1. Core Architecture

The core architecture is the “brain” of the embedded microprocessor, determining its basic computation and control capabilities, mainly including the following modules:

Processor Core:
Arithmetic Logic Unit (ALU): Responsible for executing basic arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, etc.).
Control Unit (CU): Decodes instructions and coordinates the operation of various components, ensuring instructions are executed in order.
Register File: High-speed storage unit for temporarily holding data, addresses, and status information. For example, ARM processors have 31 general-purpose registers (R0-R30), as well as special registers like the Program Counter (PC) and Link Register (LR).
Memory Controller: Manages interactions with external memory (RAM, ROM, Flash), supporting cache mechanisms to improve data access speed.
I/O Interfaces: Integrates various communication interfaces (e.g., UART, SPI, I2C) for data exchange with external devices.
Bus System: Connects data pathways between functional modules, divided into data bus (transfers data), address bus (specifies storage locations), and control bus (transmits control signals).

Example: ARM Cortex-M series processors use a three-stage pipeline design to enhance efficiency through instruction prefetching, decoding, and execution stages in parallel.

2. Instruction Set Architecture (ISA)

The instruction set is the bridge between the processor and software, directly affecting performance and power consumption:

Reduced Instruction Set (RISC):
Characteristics: Few instructions, uniform format (e.g., ARM’s 32-bit fixed-length instructions), single instruction completes in one cycle.
Advantages: Simplifies hardware design, reduces power consumption, suitable for embedded scenarios (e.g., ARM, RISC-V).
Example: ARM processors’ Load/Store architecture requires data processing to occur only between registers, with separate instructions for accessing memory.
Complex Instruction Set (CISC):
Characteristics: Rich instruction set, diverse formats (e.g., x86’s variable-length instructions), supports complex operations (e.g., a single instruction can perform memory-to-memory operations).
Disadvantages: Higher hardware complexity, greater power consumption, but still applicable in high-performance scenarios (e.g., Intel Atom embedded processors).

Comparison: RISC is more suitable for the low-power demands of embedded systems, while CISC still has a market in scenarios requiring strong compatibility (e.g., industrial control).

3. Storage Architecture

The storage architecture directly affects data access efficiency and system performance:

Instruction Memory: Stores program code, usually read-only memory (ROM) or Flash, supporting data retention after power loss.
Data Memory: Temporarily stores runtime data, using high-speed SRAM or dynamic RAM (DRAM).
Cache Mechanism: High-end embedded MPUs (e.g., NXP i.MX series) integrate L1/L2 caches to reduce main memory access latency.
Virtual Memory Management: Some processors (e.g., ARM Cortex-A series) support MMU (Memory Management Unit) for address mapping and permission protection.

Architectural Differences:

Von Neumann Architecture: Shares the same storage space and bus for instructions and data (e.g., ARM7), simple structure but suffers from “storage bottleneck”.
Harvard Architecture: Separates storage for instructions and data (e.g., ARM9/ARM11), allowing parallel access through independent buses, significantly improving throughput.

4. System Bus Architecture

The bus is the “highway” for communication within the processor and with external devices:

On-Chip Bus: Connects the CPU core with internal peripherals (e.g., DMA controllers, timers), common protocols include AMBA (Advanced Microcontroller Bus Architecture).
External Bus: Expands external memory or high-speed peripherals, such as PCIe, DDR interfaces.
Multi-Bus Design: High-end MPUs (e.g., TI AM5728) adopt multi-layer bus architecture to avoid bandwidth competition and ensure real-time performance.

Example: ARM’s AMBA bus family includes sub-protocols like AHB (high performance), APB (low power), to meet different peripheral needs.

5. Types of Architectures

Embedded MPU architectures can be mainly classified into the following categories:

Single-Core Architecture: A single processor core, suitable for lightweight tasks (e.g., home appliances, sensor nodes).
Multi-Core Architecture: Integrates multiple cores (e.g., dual-core, quad-core), supporting parallel processing to meet high-performance demands (e.g., smartphones, autonomous driving).
Heterogeneous Architecture: Combines cores with different instruction sets (e.g., ARM Cortex-A + Cortex-M), balancing high performance and real-time capabilities (e.g., industrial robots).
RISC Architecture: Uses a reduced instruction set (e.g., ARM, RISC-V), improving energy efficiency, suitable for customized designs.
Complex Instruction Set (CISC): Such as x86 architecture, strong compatibility but higher power consumption, mainly used in high-performance embedded scenarios (e.g., servers, industrial control devices).

6. Other Key Features

Low Power Design: Dynamic voltage frequency scaling (DVFS), clock gating technology (e.g., Renesas RX series sleep mode current <1μA).
Interrupt Controller: Supports multi-level priority interrupts (e.g., STM32’s NVIC), ensuring real-time response to external events.
Security Mechanisms: ARM TrustZone technology isolates secure and non-secure worlds through hardware, ensuring the security of IoT devices.

5. Mainstream Embedded Microprocessor Architectures

Architecture	Feature Description	Application Examples
ARM Cortex-A	High performance, low power, supports virtual memory	i.MX6/8, RK3568, Allwinner A40i
PowerPC	High reliability, high throughput, commonly seen in traditional industrial systems	Aircraft control systems, railways, automotive ECUs
RISC-V	Open-source instruction set, flexible and customizable, suitable for domestic and customized chips	Alibaba Xuantie, Sifive processors
MIPS	Simplified, modular, with a long history	Industrial routers, security recorders
x86 (Low Power)	Powerful functionality, high compatibility, but relatively high power consumption	Intel Atom, low-power edge gateways

6. Common Applications of Embedded Microprocessors

Smart Terminals

Android tablets, POS machines, facial recognition terminals, projectors

Edge Computing Devices

AIoT edge boxes, NVRs, industrial AI gateways, edge model inference

Industrial Control Systems

Industrial control motherboards, PLC controllers, embedded human-machine interfaces (HMI)

Vehicle Systems

Vehicle central control, ADAS controllers, camera image preprocessing

9. Selection and Usage Recommendations

1.Is it necessary to run a Linux system?

Yes → Choose MPU (e.g., Cortex-A)
No → MCU may be sufficient (e.g., STM32)

2.Is external large-capacity storage/screen/network required?

Yes → MPU has clear advantages (supports DDR, USB, HDMI)

3.Is there a need for AI acceleration?

Yes → It is recommended to choose an MPU that supports NPU (e.g., RK3588, i.MX 93)

4.Are there strict power consumption limits?

Yes → Prioritize low-power MCUs / ultra-low-power MPUs (e.g., Cortex-A7)

10. Technical Trends

Multi-core Heterogeneity: Combining CPU, GPU, NPU (Neural Processing Unit) for AI acceleration (e.g., NVIDIA Jetson series).
Rise of Open-source Architectures: RISC-V is gradually penetrating industrial and consumer electronics fields due to its flexibility and low cost.
Integration of Edge Computing: MPUs integrated with AI accelerators (e.g., TPU) support real-time data processing (e.g., AI recognition in security cameras).
Low Power Optimization: Further reducing energy consumption through advanced processes (e.g., 5nm) and asynchronous clock designs.
Enhanced Security: Integrating hardware encryption engines (e.g., ARM TrustZone) to ensure the security of IoT devices.

Conclusion

The embedded MPU serves as a bridge connecting general processors and application-specific integrated circuits (ASICs), combining high performance and flexibility. With the rise of IoT, artificial intelligence, and edge computing, MPUs are evolving towards multi-core heterogeneity, low power consumption, and high security, becoming the core driving force behind smart devices. When selecting an MPU, it is essential to consider performance requirements, power consumption limits, costs, and ecosystem support (e.g., development tools, operating system compatibility).