Virtualization Features of Cortex-R52 Architecture

About ARM Cortex

The ARM Cortex series is divided into three categories: Cortex-A, Cortex-R, and Cortex-M.

Among them, processors based on Cortex-A are suitable for running systems with extremely high performance requirements. If high performance is required while ensuring real-time capabilities, it is suitable to use Cortex-R architecture chips. Cortex-M is suitable for other applications in embedded system microcontrollers.[1]

About ARM Cortex-R52

As the first R core processor based on the ARMv8-R architecture, the Cortex-R52 has 4 cores, uses a 16nm process, and has a maximum clock frequency of 1.6GHz.[2]

Virtualization Features of Cortex-R52 Architecture

The R52 is a 32-bit high-performance real-time processor with extremely high functional safety standards and great flexibility. The 4 cores can operate independently or be configured as up to 4 cores in lock-step or split-lock. The R52 has a two-level MPU, each capable of setting 24 partitions, with a minimum partition size of 64 bytes.

The Cortex-R52 supports hardware-enforced software separation features to ensure that code requiring absolute security is completely isolated. This allows the hardware to be managed by a software manager to supervise task execution and resource allocation. Through precise and thorough software separation, the Cortex-R52 reduces the amount of code that must undergo security certification, simplifies software integration, maintenance, and verification, thereby accelerating the R&D process.[3]

NXP S32Z and ST SR6P7G7

Recently noted, the S32Z adopts the Cortex-R52 architecture, while the SR6P7G7 uses the upgraded Cortex-R52+ version. (For differences between R52/R52+, please refer to the link[4].)

Virtualization Features of Cortex-R52 Architecture
Virtualization Features of Cortex-R52 Architecture

This article does not provide a specific interpretation of these two chips, but in scenarios where these two chips are selected, users should not miss the new features based on ARMv8-R, namely the virtualization features, which can help developers effectively and reasonably integrate the functions of multiple traditional distributed ECUs into a single controller[5]. For example, based on this feature, developers can isolate different functional safety level requirements, information security level requirements, and software that requires OTA upgrades into different virtual machines for strong isolation.

Virtualization Features of Cortex-R52 Architecture

Two Types of Virtual Machines?

Due to slight differences in the definitions of embedded virtual machines from different sources, technically, they are mainly divided into two types: Hypervisor and Separation Kernel.

Hypervisor

A Hypervisor, also known as a virtual machine monitor (VMM), is computer software, firmware, or hardware that can create and run virtual machines. The computer used by the hypervisor to execute one or more virtual machines is called the host machine, while these virtual machines are referred to as guest machines. The hypervisor provides a virtual operating platform to execute guest operating systems, managing the execution phases of other guest operating systems; these guest operating systems share the virtualized hardware resources.[6] Since the hypervisor separates each virtual machine, actions within one virtual machine do not affect others.

Virtualization Features of Cortex-R52 Architecture

From the perspective of VM resource usage, hypervisors can be divided into two categories: Type-1 and Type-2. Type-1 hypervisors run directly on physical hardware (sometimes referred to as bare-metal hypervisors or native virtual machines), while Type-2 hypervisors run directly on an operating system (which runs on physical hardware).[7]

Type-1 hypervisors require hardware support and have high operating efficiency, while Type-2 hypervisors run like other computer programs on an operating system and have lower efficiency compared to Type-1.[6]

Virtualization Features of Cortex-R52 Architecture

The hypervisor provides virtualization of hardware resources, which can be divided into full virtualization technology and paravirtualization technology based on different technologies. The difference is that paravirtualization requires modification of the Guest OS, allowing some API operations to interact directly with the hardware without needing translation through the hypervisor.

Virtualization Features of Cortex-R52 Architecture

Full Virtualization Technology

Virtualization Features of Cortex-R52 Architecture

Paravirtualization Technology

Separation Kernel

Regardless of the type of hypervisor used, a certain amount of system resources will be consumed to provide virtualization technology. To introduce the concept of virtual machines in the embedded field (which can also be referred to as partitioning), a special type of hypervisor is the Separation Kernel.

The separation kernel only provides isolation without device drivers/user models/shell access/dynamic memory. If needed, these are all implemented in the guest programs within the virtual machine. Thus, the separation kernel can be very streamlined, defining fixed virtual machines (and allocating resources), and controlling message interaction flows.[8]

Virtualization Features of Cortex-R52 Architecture

The advantage of the streamlined code of the separation kernel is that it is easier to implement and verify that it is secure, which is particularly important in current automotive systems that require high levels of functional safety. Since virtualization is not required, operations on hardware by virtual machines do not require kernel translation. If there are no message requests between virtual machines, the separation kernel can even be considered “non-existent” during runtime, and each virtual machine can maintain real-time performance without differences compared to before.

Why Cortex-R52?

As mentioned earlier, to run multiple programs on a single MCU, a hypervisor, guest OS (in VM), and upper-layer applications are required. To have different control permissions over hardware resources, the Cortex-R52 (based on ARMv8) provides three levels of Exception levels, namely EL0-EL2.

Virtualization Features of Cortex-R52 Architecture

Exception Level

EL0 has the lowest software execution privilege, also known as non-privileged execution, while EL1 and EL2 have higher software execution privileges. At the EL2 level, processor virtualization features are provided. Triggering an exception or returning from a specific exception allows software execution to transfer between different ELs. Triggering an exception can only trigger the current level or a higher-level exception and cannot downgrade; if returning from a specific EL, it can only remain at the current EL level or drop to a lower-level EL. Additionally, it is not possible to trigger an exception targeting EL0.[9]

Thus, generally, the hypervisor runs at the EL2 level, providing processor virtualization, the guest OS runs at the EL1 level, and various upper-layer application programs run at the EL0 level.

Two-Level Memory Protection

In addition, the R52 (or ARMv8-R core) supports a two-level MPU, with the EL-1 MPU functioning similarly to the MPU used in other chips. However, the newly added EL-2 MPU can provide storage access protection at the EL2 level (stage 1) and can also protect storage access requests from EL1/EL0 levels (stage 2). The R52 supports two-level protected address translation.

Interrupt Virtualization

The HCR (Hyp Configuration Register) and GIC (Generic Interrupt Controller) will use virtual interrupts.

The hypervisor uses virtual interrupts to distribute interrupts to the corresponding guest OS. For the guest OS, handling interrupts is no different from handling physical interrupts.

Virtual interrupts can only be created at the EL2 level.

Virtualization Features of Cortex-R52 Architecture

If HCR is set, exceptions captured by the hypervisor will cause the CPSR register’s F (FIQ mask bit)/I (IRQ mask bit)/A (Asynchronous (imprecise) abort disable bit) flags to be ignored when the exception is captured at EL1/EL0, and the program will immediately jump to the corresponding EL2 exception handler.

When an exception is configured to be captured at EL2 and occurs during the execution of EL2/EL1/EL0 programs, the F/I/A flag will take effect. F/I/A acts as a mask to determine whether virtual interrupts from EL1/EL0 or physical interrupts from EL2 will be treated as exceptions.

If HCR is not set to capture exceptions, exceptions occurring at EL1 will still be handled by EL1.

Virtualization Features of Cortex-R52 Architecture

For the GIC, it will distribute interrupts, for example, forwarding shared peripheral interrupts (SPI) generated by peripherals to a specific core, or distributing software generated interrupts (SGI) triggered by a core to another core for inter-core communication.

In addition, there are private peripheral interrupts (PPI) that can only exist in a specific core and cannot be received by other cores.

Due to the existence of virtual interrupts, the GIC can associate a physical interrupt with a virtual interrupt and distribute it to a specific core. Virtual interrupts can exist independently and do not need to correspond to physical interrupts.

Virtualization Features of Cortex-R52 Architecture
Virtualization Features of Cortex-R52 Architecture

Virtual Timer

Different guest OSs have their own virtual timers, which only record time when their respective guest OSs are active. For example, within a 10-second timeframe, if two guest OSs each execute for 5 seconds, their respective timers will only record 5 seconds of time.

Virtual Machine ID

To distinguish different virtual machines, the hypervisor assigns different IDs to each virtual machine. When the guest OS accesses peripherals, ID information will be present on the bus, allowing requests to be filtered based on access restrictions. Each device or register is protected by the SMPU (System Memory Protection Unit).

Register Backup

An important part of creating a virtual machine is that the guest OS can be paused and then resumed. When paused, the state of the virtual machine must be saved and backed up by the hypervisor. If the guest OS execution needs to be reactivated, the hypervisor will restore the register information from the backup. As shown in the two images below, Action1/2 alternately execute.

Virtualization Features of Cortex-R52 Architecture
Virtualization Features of Cortex-R52 Architecture

EB/Vector/ETAS Products?

Due to limited focus areas, only a few MCU-end hypervisor products provided by AUTOSAR vendors are recorded here.

Virtualization Features of Cortex-R52 Architecture

EB: EB tresos Embedded Hypervisor – Elektrobit (Separation Kernel/Hypervisor)

ETAS: RTA-LWHVR – RTA Software Products – ETAS (Separation Kernel/Hypervisor)

Vector: Safe and Efficient Virtualization With MICROSAR Classic veHypervisor | Vector (Separation Kernel/Hypervisor)

The annotations in parentheses are inferred from the official page content regarding the supported range of their products; please correct any errors.

References

  1. ^Which ARM Cortex Core Is Right for Your Application: A, R or M? https://www.silabs.com/documents/public/white-papers/Which-ARM-Cortex-Core-Is-Right-for-Your-Application.pdf

  2. ^Cortex-R52 Technical-Specifications https://developer.arm.com/Processors/Cortex-R52#Technical-Specifications

  3. ^ARM Launches Safety Processor Cortex-R52 for Autonomous Driving https://www.eet-china.com/news/201609210921.html

  4. ^What are the major differences between Cortex-R52 and Cortex-R52+ https://developer.arm.com/documentation/ka005377/1-0/?lang=en

  5. ^Efficient Multi-ECU Integration: Multi-Application Development Based on NXP S32 Real-Time Processors and Virtual Machines https://www.nxp.com.cn/pages/multi-application-hosting-and-virtualization-on-s32-real-time-processors-for-effective-multi-ecu-consolidation:TIP-S32ZE-TRAINING-CN

  6. ^abHypervisor https://en.wikipedia.org/wiki/Hypervisor

  7. ^Embedded Virtualization Technology http://www.prtos.org/embedded-hypervisor/

  8. ^WHAT IS A SEPARATION KERNEL? https://www.lynx.com/embedded-systems-learning-center/what-is-a-separation-kernel

  9. ^Exception levels https://developer.arm.com/documentation/100026/0104/Programmers-Model/Armv8-R-AArch32-architecture-concepts/Exception-levels?lang=en

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