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The semiconductor manufacturing process can be divided into front-end and back-end processes. The front-end process mainly involves wafer manufacturing, while the back-end process primarily includes packaging and testing. Among these, packaging (Package) refers to the process of connecting tested integrated circuit bare chips (Die) to external circuits through a series of technical means, providing physical protection and environmental isolation through packaging materials, ultimately forming a standalone electronic device that can be installed and operated.
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There is a significant difference between advanced packaging and traditional packaging processes. Advanced packaging introduces new applications including wafer thinning, RDL production, Bump production, TSV production, etc. The semiconductor packaging equipment required consists of existing back-end packaging equipment and newly added front-end equipment.
New front-end equipment and existing back-end equipment for advanced packaging
Technological upgrades of traditional back-end equipment under advanced packaging
Thinning Machine
The wafer thinning machine (Wafer Thinning Machine) is a key piece of equipment in semiconductor manufacturing, primarily used for thinning semiconductor wafers to meet the requirements of subsequent processes (such as packaging and testing). Its core functions include reducing wafer thickness, improving surface quality, and adapting to advanced packaging. The wafer thinning process involves mechanically or chemically grinding the back of the wafer to reduce its thickness to a suitable level for packaging. The principle mainly involves methods such as mechanical grinding, chemical mechanical polishing, wet etching, and dry etching to remove material from the wafer surface. During the thinning process, strict control of the wafer’s flatness and thickness is required to ensure the quality and performance of the wafer. The wafer thinning machine is the key equipment for achieving the wafer thinning process.
The typical technical flow of wafer thinning usually includes several key steps: preparation, wafer fixation, rough grinding, fine grinding, polishing (optional), cleaning, inspection, and subsequent processing. The wafer thickness is generally about 750μm, and it can be thinned to around 100μm (the thickest wafers used for logic gates have a thickness of 100µm) to ensure mechanical stability and prevent warping during high-temperature processing. With the increasing application of 3D packaging, the requirement for wafer thickness to be reduced to 50-100μm or even below 50μm significantly increases the quality demands for thinning equipment. Additionally, DRAM memory typically requires wafers with a thickness of 50μm, while MEMS memory usually has a thickness of about 30μm.
Die Saw
The wafer die saw is a device that uses blades or lasers to cut wafers containing many chips into individual die pieces. It is a key piece of equipment in the wafer cutting and WLP cutting stages of semiconductor back-end packaging and testing. The quality and efficiency of the cutting directly affect the quality of the chips and production costs. Depending on the wafer process and product requirements, a single wafer typically consists of hundreds to thousands of small chips, with most wafers having a gap of 40μm-100μm between the dice, known as the cutting path. 99% of the chips on the wafer have independent functional modules (1% are edge dice, which do not have usable performance). To separate the small chips into individual dice, cutting processes are required. The die cutting process mainly includes blade cutting and laser cutting, with laser cutting further divided into traditional laser cutting and laser stealth cutting. Traditional laser cutting requires a protective coating on the wafer surface, followed by applying high-energy laser to cut the silicon along the cutting grooves; while stealth laser cutting first uses laser energy to cut the interior of the wafer, then applies external pressure to the tape attached to the back, causing it to break and thus separate the chips.
In the context of advanced packaging, the application trend of laser cutting (especially laser stealth cutting) significantly surpasses traditional blade cutting, with core advantages including: 1) meeting the demand for high precision and low damage, protecting micro-nano structures in advanced packaging; 2) flexibly adapting to complex designs, such as thin wafers, heterogeneous integration, and 3D stacking.
Pick and Place Machine (Die Bonder)
The pick and place machine (Die Bonder), also known as a die attach machine, picks chips from the already cut wafers (Wafer) and places them on the corresponding die flag on the substrate, using silver glue (Epoxy) to bond the chip and substrate together. The pick and place machine can place components at high speed and high precision, achieving key steps such as positioning, alignment, flip-chip, and continuous placement. Packaging pick and place machines are divided into FC packaging pick and place machines, FO packaging pick and place machines, and 2.5D/3D pick and place machines. According to application types, they can be classified into IC die bonders, discrete device die bonders, and LED die bonders (pick and place die bonders and COB die bonders), mainly used in the packaging processes of semiconductor chips, optical chips, optical modules, silicon photonic devices, sensors, etc.
Due to advanced packaging technologies such as 3D stacking, system-in-package (SiP), and fan-out wafer-level packaging (FOWLP) requiring the handling of smaller components, denser layouts, and more complex structures, higher demands are placed on the precision and efficiency of pick and place machines. In terms of precision, the current domestic IC die bonders generally have a precision of ±25μm or more, while the international leading level is ±3~5μm, with high-end models reaching ±1μm (such as ASMPT COS pick and place machines). Under the demand for advanced packaging, 3D NAND, HBM, etc., require precision to reach ±1~3μm to ensure accurate alignment and increased interconnection density between chips and substrates; in terms of efficiency, the current domestic equipment has a UPH of about 12-15K, while international leading models of medium to high precision equipment can reach UPH of 15-20K, and high-speed models (such as ASMPT FC/FB series) can exceed 25K. In advanced packaging production lines, to meet high capacity demands, UPH needs to be increased to over 20K, even 30K.