Innovations in RISC-V: Standing on the Shoulders of Giants

RISC-V is also known as “the Linux of CPUs.” For some, this title feels like a legacy and an innovation at the same time, especially if you are a staunch believer in open source. However, I am a true pragmatist, and the excessive marketing of RISC-V has made me lose interest in the term.

It wasn’t until I began to study RISC-V in detail that I realized that becoming the Linux of some microprocessors might be one of RISC-V’s least publicized advantages.

In the following article, I will delve deeper into the innovations of RISC-V. Standardizing open source is something many frameworks are already doing, so it’s not new; it’s the characteristics and openness based on its architecture design that highlight RISC-V’s innovative power.

However, adhering to old ideas is not due to a lack of imagination or innovation failure among RISC-V designers. On the contrary, they deliberately want to use proven instructions and designs from existing architectures.

There are many reasons for this. For instance, many novel and overly “clever” choices in the past have become outdated in future microarchitecture innovations.

In contrast, RISC-V’s innovations perfectly embody the idea of taking the essence and discarding the dross to ensure the minimalism of the instruction set. Lessons learned from the past have made them aware that future support for both compressed instructions and 64-bit instructions is needed.

Secondly, minimalism benefits performance because smaller and simpler chips are easier to increase clock frequency. A small company named Micro Magic has manufactured a RISC-V chip that can run at 0.07w of power.

In contrast, the Apple M1 chip runs at 10w of power. The Micro Magic chip can achieve clock frequencies up to 5 GHz.

At first glance, the term “concise” should not be used to describe RISC-V. But in reality, the compressed instruction set and 64 bits instructions were preset for scalability from the beginning. The basic instruction level was designed with the consideration that there would be a 64-bit extension, which previous designs did not account for, so 32-bit instructions had to be repeated for 64 bits. In contrast, most existing instructions on RISC-V only work on 64-bit registers rather than using 32-bit registers on a 64-bit RISC-V CPU. Therefore, the 64-bit extension on RISC-V is actually just adding special instructions to handle the 32-bit part of the 64-bit registers.

For example, ADDW and SUBW instructions are used to store 32-bit results in the target register. The normal ADD and SUB instructions add and subtract 64-bit numbers on a 64-bit CPU and 32-bit numbers on a 32-bit CPU.

This means that the 64-bit code on RISC-V looks almost the same as the 32-bit code.

The compressed instruction set is a similar extension instruction set that allows two instructions to fit within a 32-bit byte, while other frameworks can only squeeze them in a clumsy way. For instance, in ARM, the Thumb2 compressed instruction format is essentially a different ISA, rather than an extension on RISC-V. This means the CPU must switch modes internally and use different decoders. This adds complexity. In contrast, decoding compressed RISC-V instructions is very simple. Converting them to 32-bit instructions only requires 400 logic gates (AND, OR, NOR, NAND gates). This is just the tip of the iceberg.

The minimal RISC-V CPU implementing the basic instruction set only used 8000 logic gates.