Differences Between RISC-V+AI and AI+RISC-V

Many domestic chip companies have chosen to adapt quickly to market demands by being compatible with the CUDA ecosystem. While this is effective in the short term, in the long run, this “if you can’t beat them, join them” approach remains constrained by human limitations. Other companies choose the path of independent development but face high development costs and a shortage of talent, putting them at a disadvantage in market competition.

Against the backdrop of rapid global development in artificial intelligence (AI) technology, the combination of RISC-V and AI has become a focal point of industry attention. Despite significant advancements in hardware performance of domestic AI chips, they still face enormous challenges in software ecology. Especially when compared to NVIDIA’s CUDA ecosystem, domestic AI chips appear weak in terms of ecosystem—since its launch in 2006, CUDA has invested a cumulative $12 billion into its ecosystem and has 4.5 million developers, forming a powerful software ecosystem.

Differences Between RISC-V+AI and AI+RISC-V

In contrast, other AI computing software ecosystems exhibit a small, fragmented, and weak situation, with inadequate investment in domestic AI chip software ecosystems, leading to a lack of core competitiveness. Although there are over 40 high-end AI chip companies in China, they are fighting their own battles at the software stack level, unable to form a cohesive force, resulting in an overall market share of less than 10%.

Recently, the fourth China RISC-V Industry Forum was held by the beautiful Dushu Lake in Shanghai. Professor Xie Tao from Peking University, who is also the chairman of the Artificial Intelligence and Machine Learning Committee of the RISC-V International Foundation, delivered a speech titled “The Path of RISC-V+AI in the Era of Intelligent Connectivity,” providing an in-depth analysis of the combination of RISC-V and AI technologies and their development paths.

Professor Xie Tao from Peking University, chairman of the Artificial Intelligence and Machine Learning Committee of the RISC-V International Foundation

Currently, many domestic chip companies choose to quickly adapt to market demands by being compatible with the CUDA ecosystem. While effective in the short term, in the long run, this “if you can’t beat them, join them” approach remains constrained by human limitations. Other companies that choose the path of independent development face high development costs and a shortage of talent, putting them at a disadvantage in market competition.

Opportunities for RISC-V+AI Development

In the mobile device sector, Android once challenged Apple’s closed ecosystem with its diverse hardware choices in an open ecosystem, freedom of open source code, and extensive application services. Thus, it has been suggested: can we borrow from the Android model that shocked the iOS ecosystem to shake up the CUDA ecosystem?

In this regard, Professor Xie Tao believes that under such circumstances, RISC-V, due to its openness, flexibility, and high scalability, has become an ideal choice in the AI chip field. The RISC-V architecture allows chip designers to customize AI accelerators based on specific needs, which is particularly suitable for addressing the rapidly changing AI workloads and is expected to become a force that shakes the CUDA ecosystem.

Moreover, the RISC-V instruction set can be expanded as needed to enhance the performance and efficiency of AI computing. These advantages give RISC-V a significant edge in low power consumption and high efficiency, especially in application scenarios such as edge computing and smart terminals.

Professor Xie Tao quoted Sun Ninghui’s three models of the new information technology system proposed in the “Bulletin of the Chinese Academy of Sciences”:

A System (High-speed Rail Model), where the mainstream platform of our informationization is dominated by the X86 and Arm ecosystems. Domestic processors like Haiguang and HiSilicon emphasize “full compatibility”—”Without you, I can’t function”;
B System (Beidou Model), emphasizing “full autonomy” with Loongson and Shenwei as representatives. Because they do not comply with mainstream market compatibility, their ecosystems are weak—”Without you, I can barely manage”;
C System (5G Model), taking the “fully open” approach, with the whole world building the ecosystem together, where no one controls anyone, and no one can restrict anyone, such as RISC-V—”You contain me, and I contain you”.

Professor Xie Tao stated that adopting the A system means joining the CUDA camp (e.g., Birun/Alibaba Tsinghua), which would keep R&D in a “following” state, being led by others, and facing numerous patents that are difficult to bypass, relying solely on open-source compilers to avoid litigation. While it is easier to acquire customers, this actually strengthens the CUDA ecosystem; if choosing the B system, it requires adopting custom programming languages (like Huawei Ascend/Cambricon), which has the drawback of being costly, as each company needs to maintain a complete software engineering team, accumulating decades of R&D investment. The talent in system software, programming languages, and compilers in this industry is already scarce, which leads to a dispersion of power, with each company fighting its own battles, making it difficult to form an effective force to compete with CUDA.

Therefore, Professor Xie Tao believes that RISC-V represents the C system, which is the fully open path. “Building AI computing power based on RISC-V is an inevitable trend and a global consensus.”

Main Models of RISC-V AI Chips

On April 11, 2024, the RISC-V International Foundation Council announced in the foundation community that the top strategic priorities for the RISC-V International Foundation in 2024 will be: artificial intelligence/machine learning, security, and automotive.

AI represents a significant opportunity for RISC-V, just as the PC did for the x86 ecosystem, and mobile phones did for the Arm ecosystem.

The advantages of building AI computing power based on RISC-V lie in its openness, flexibility, high scalability, power consumption, and efficiency advantages, along with strong support from the ecosystem and community. The simplified instruction set and customizable extensions of RISC-V can meet the rapidly changing demands of AI workloads while enhancing computing speed and energy efficiency.

Professor Xie Tao further introduced the two main models of RISC-V AI chips:

Integrated Model (Tightly Coupled): Suitable for low-power fields (RISC-V+AI). It uses the CPU backbone as a skeleton, integrating AI computing units within the CPU, sharing pipeline units such as the program counter and register file, while only adding matrix or vector units in the execution unit.

Tightly Coupled Model

Attached Model (Loosely Coupled): Suitable for high-computing power fields (AI+RISC-V). The AI computing unit is external to the CPU, with its own independent pipeline, register file, cache, etc. It acts as a “coprocessor,” capable of receiving instructions from one or more CPUs and asynchronously executing tasks submitted by different CPUs.

Loosely Coupled Model

Strategic Thinking to Address Challenges

In response to the fragmented ecology, severely insufficient resource investment, lack of organizational coordination, and weak collaboration between industry, academia, and research in the RISC-V+AI ecosystem in China, Professor Xie Tao proposed a comprehensive strategy from the ground up, from edge to cloud, focusing on tool innovation, and shared several core strategies:

Bottom-Up Approach: Expand the RISC-V AI instruction set (promoting it to RISC-V International Foundation standards) + use an open-source system software stack as a public open-source root to leverage international open/open-source communities to grow leaves (commercial software/chips based on open-source roots), forming a technical ecological layout of “root technology open-source” and “leaf technology competition”.

From Edge to Cloud: Focus on edge/terminal sides (diverse, fragmented, and large-scale computing scenarios, such as smart terminals, AI PCs, etc.) to promote the development and application of the software ecosystem, thereby driving the software ecosystem in the cloud.

Tool Innovation: Relying on the increasingly powerful RISC-V hardware and software ecosystem, focus on global open-source tool innovation.

Specific Strategies to Break the Deadlock

Professor Xie Tao proposed specific strategies to break the deadlock through the dual approaches of international standards and open-source communities:

Using International Standards to Leverage International Resources: Grasp the “root technology” and quickly layout new markets (smart terminals, AI PCs, etc.) based on consensus from leading enterprises in China, promoting international foundation standards to rely on upstream international open-source communities to contribute system software stacks.

Building an International Open-Source Software Ecosystem: Contribute to the emerging international open-source software ecosystem (Triton/SYCL), voicing strong messages from China and showcasing China’s large scale and strong technology.

The international standards refer to the RISC-V AI extension instructions, and the open-source software/chips refer to Triton, SYCL, and RISC-V AI chip IP. “Promoting RISC-V+AI international standards is a means, and the ultimate goal is the system software stack,” Professor Xie Tao said.

The advantage of using Triton is that hardware manufacturers only need to focus on how to compile from the Triton layer to hardware code to efficiently support various AI frameworks (such as PyTorch, JAX, etc.) above. Compared to CUDA, Triton has lower programming difficulty, higher implementation efficiency, and lower ecological compatibility burden while still achieving performance close to the extreme optimization of CUDA, surpassing the direct use of the PyTorch API.

Speaking of SYCL, Professor Xie Tao vividly compared: “CUDA is the x86 of programming models, while SYCL is the RISC-V of programming models.”

In contrast, closed architectures/ecosystems represented by x86 and CUDA cannot be redeveloped or expanded without authorization, and their monopoly model places technology completely in the hands of American oligarchs. This model, after a long period of sedimentation, has the best compatibility and the deepest technical accumulation, but China has weak technological accumulation in this field, making it difficult to transfer optimization of software and hardware system design to other architectures.

On the other hand, RISC-V and SYCL do not have authorization issues, and the direction of technology is determined by the open-source community (compiler community, programming model community). Although their compatibility is the weakest and their technical accumulation is the shallowest, the technological accumulation of various countries is on par, and optimizations in the design of software and hardware collaboration are easily transferable to other architectures.

Launch of the Jiachen Plan

Before the Spring Festival of 2024, ASE, PLCT, and Suan Neng Company jointly initiated the “Jiachen Plan.” It is reported that the vision and mission of the “Jiachen Plan” is to establish an open standard system and open-source system software stack covering the entire information industry from data centers to desktop offices, from mobile wearables to smart IoT before the next Bingchen year (the Year of the Dragon in 2036), to ensure that the maturity of the RISC-V software and hardware ecosystem reaches or exceeds that of other mainstream architectures.

The goals of the plan mainly include the following:

1. Unite over 100 processor and solution vendors, and over 500 software companies to complete adaptation and optimization for RISC-V in more than 18 key industry sectors, collaborating to port and deploy over 1000 important industry and commercial software.

2. Focus on high-performance RISC-V processors and IP, such as SG2380 and Xiangshan, to assist the industry in completing commercially deliverable industry solutions based on RISC-V, including but not limited to intelligent computing acceleration, edge computing, storage, robotics, industrial simulation, and medical assistance.

3. Establish a RISC-V talent recognition system connecting over 10,000 professionals with expertise in RISC-V hardware design, software development, community operation, and education and training, achieving mutual recognition and cooperation in the field of RISC-V talent.

Currently, over 40 open-source community enterprises have joined the plan, and Professor Xie Tao has also called on everyone to participate in building the open-source software and hardware ecosystem for RISC-V.

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