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1) High Flexibility, Suitable for High-Speed Iteration Scenarios (can be “frequently modified”): By simply changing the LUT mask in the FPGA, a single FPGA can take on the functionality of another circuit. Therefore, FPGA can realize any circuit function, and the modification time may not exceed one second, with no limit on the number of modifications. This is the characteristic of FPGA’s extremely high flexibility. This feature of FPGA is particularly suitable for the following four scenarios:a) Industries where standards/protocols/algorithms frequently change, requiring support for reconfigurable systems, such as wireless communication protocols that change frequently, data center interconnections that need to be compatible with various protocol standards, rapid iterations of neural network algorithms, military communication encryption methods that change often, and dynamic reconfiguration of processing systems in orbiting spacecraft. In similar scenarios, using FPGA can save a lot of time and R&D costs;b) Fast iteration, cost-sensitive industries, because they are available “on-site”. Compared to ASICs, FPGAs do not require a three-month to one-year tape-out cycle, resulting in shorter time-to-market, which is especially important for competitive and rapidly iterating industries like consumer electronics. Since 2000, companies like Lattice and Xilinx have launched many mid-to-low capacity FPGAs priced around $2.5 for the consumer electronics market;c) Small batch industries, where the MASK (photomask) costs during chip R&D are fixed costs (MASK, also known as photomask, is used to manufacture the various layers of integrated circuits, such as N-well, active areas, polysilicon, metal layers, etc. Manufacturing a chip usually requires multiple MASKs corresponding to different process layers. If the chip design fails or the process validation does not pass, this cost cannot be recovered). For 65nm, it costs 2 million RMB, for 45nm it costs 4.3 million RMB, and for 28nm it costs 10 million RMB. As the process technology improves, the risk of failure increases. For scenarios with an annual demand of < 5 million units, developing ASICs/ASSPs specifically for a certain application makes it difficult to amortize the huge R&D costs. Although FPGAs have a higher unit price, they can realize any circuit function, saving tens of millions in chip R&D costs, making them particularly suitable for small batch products, such as in defense and aerospace fields;d) Designs that require repeated modification and verification, for example, in the prototype design of ASICs/ASSPs, FPGAs are almost always used for verification to identify issues in the design and make timely modifications, thus avoiding the risk of multiple tape-outs as much as possible. Chip prototype simulation is one of the “must-haves” for FPGAs and is the fundamental reason for their existence. The highest-end FPGAs are often sold to large digital chip companies like Intel for verification of their next-generation products, and this demand continues to support FPGAs at the forefront of technology nodes.2) Good Parallelism, Suitable for Scenarios Requiring Low Latency and High Parallel Computation (“calculates quickly”): The hundreds of thousands of CLBs inside an FPGA can work independently at the same time. Even with a lower clock frequency, its computational efficiency far exceeds that of several efficient units, making it particularly suitable for signal processing scenarios that involve a lot of parallel computation. Additionally, since there are no thread or resource conflict issues, the latency of FPGAs is deterministically low, making them particularly suitable for low-latency scenarios. Such scenarios are widely present in various industries, for example:a) Communication industry base stations, whether RRU/AAU, BBU/DU/CU, or even core network devices, all require the use of FPGAs to implement functions such as Turbo coding and protocol processing acceleration. In wireless signal measurement instruments priced at hundreds of thousands or even millions of RMB, high-end FPGAs priced at tens of thousands are also used for signal processing control;b) Defense and military industry, typical scenarios include radar data processing, which must meet characteristics of high capacity, low latency, and high reliability to achieve microsecond-level processing requirements, and this latency and stability requirement can only be met by FPGAs. In inertial navigation systems using fiber optic gyroscopes, FPGAs can control optical signals with low latency to achieve high precision and high dynamics measurements;c) Industry: Due to the large number of low-latency scenarios in industry, the application of FPGAs in the industrial field is very extensive, commonly seen in servo motor drives, often adopting a CPU + FPGA architecture to achieve microsecond-level control loop feedback. For example, Xilinx’s Zynq series (SoC FPGA) has a wide range of applications in industry. Additionally, FPGAs are also used in laser devices for signal control of picosecond/femtosecond lasers;d) Automotive: A typical application in the ADAS field, as FPGAs have lower latency than GPUs, ensuring better braking distances. In addition, FPGAs are also used in scenarios such as rearview mirrors;e) Security & Video: Mainly applied in front-end data collection and low-latency processing of security HD video, and are also widely used in LED displays;f) AI: Deep learning models often involve a large number of multiplications and accumulations, making them particularly suitable for using FPGAs for parallel computation to accelerate training speed.
Compared to ASICs and ASSPs, the most prominent advantage of PLDs is high flexibility. For users designing electronic systems (e.g., Huawei), there are three choices for the chips used in their products: design an ASIC themselves, purchase ASSPs from companies like Qualcomm or STMicroelectronics, or buy PLDs from Xilinx. The difference between ASICs and ASSPs is that ASICs are designed for a single user for a single application, with functionality defined by the user, while ASSPs are designed for multiple users, with functionality defined by the chip manufacturer rather than the user, thus requiring unified standards. ASIC design is time-consuming and costly, but it can achieve optimal performance and lowest power consumption for the target application. The design process for ASSPs is similar to that of ASICs but is more general, capable of balancing performance and power consumption across multiple application scenarios. Once manufactured, the functions of ASICs and ASSPs are fixed, while PLDs represented by FPGAs can have their functions modified repeatedly. Although they may not achieve optimal performance, their flexibility is unmatched by ASICs and ASSPs.
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