Implementing Post-Quantum Cryptography (PQC) with FPGA

One of the most remarkable advancements in today’s high-tech field is that quantum computing is gradually transitioning from theory to reality. After decades of theoretical exploration and technological accumulation, this disruptive and extremely complex new computing paradigm has achieved a series of substantial breakthroughs in recent years. Quantum computers perform calculations by flipping the charge of individual atoms and utilizing quantum entanglement to exist in multiple states simultaneously. Their operational methods and speeds are sufficient to solve extremely complex problems that could take years or even centuries to compute using traditional computers.

Despite the immense potential of quantum computers, they also pose new challenges and concerns for fields such as cryptography. In modern computing systems, cryptography uses complex mathematical algorithms to encrypt data in processing. Therefore, a digital key is required to decrypt and access this data.The challenge posed by quantum computing is that both the underlying algorithms used for data encryption and the mechanisms for generating and exchanging digital keys may no longer be secure in the face of quantum computers. This means that attackers could potentially reverse the encrypted data and obtain the information contained within.

Undoubtedly, this constitutes a severe challenge. A large number of enterprises, governments, and organizations worldwide still rely on traditional algorithms to encrypt massive amounts of data and depend on public and private key distribution mechanisms that have security vulnerabilities. To ensure the security of this data, the industry has developed new encryption methods and key exchange protocols that can withstand quantum computing attacks, collectively referred to as post-quantum cryptography (PQC).

Currently, the industry generally believes that quantum computers will not truly possess this decryption capability for several years (2030-2035). However, a more pressing threat is that many attackers have already begun to steal encrypted data, intending to decrypt it when future quantum computers can break existing encryption systems. This attack method, known as “harvest now, decrypt later” (HNDL), poses a particularly severe threat to confidential information, account information, and other data that require long-term confidentiality for governments or military organizations.

In light of this, governments of major countries around the world have formulated or are actively developing new algorithms, technical processes, and compliance requirements to mitigate the potential risks posed by quantum computing. For example, the National Security Agency (NSA) of the United States has established the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) policy framework, while the National Institute of Standards and Technology (NIST) has established the FIPS 202/203 standard system to address such issues. These widely adopted norms and standards not only integrate various quantum-safe encryption algorithms but also support cutting-edge cryptographic technologies such as lattice-based cryptography and hash-based digital signatures. According to the plan, some core industries and application scenarios will implement the new regulations by the end of this year, with plans for broader critical deployments by 2027.

However, policies and algorithms alone are far from sufficient; post-quantum cryptography (PQC) must also be deployed on computing devices and software platforms to ensure operational capability. This may seem simple, but it actually requires establishing a multi-layered security protection system that encompasses device authentication (i.e., declaring device functions and capabilities), firmware update security requirements, hardware trusted roots for storing keys, and ultimately extending to the entire chip manufacturing process in a secure environment.

In other words, to fully realize post-quantum cryptography (PQC), it is not enough to simply integrate dedicated chips that support new encryption algorithms and key exchange protocols into computing devices. For example, a key aspect of the key exchange process is ensuring the trustworthiness of each device in the computing chain. This requires devices to be equipped with embedded authentication software at the firmware level, which autonomously verifies device identity through a unique ID implanted during the chip manufacturing stage.

The encryption/decryption process typically occurs when the device is first powered on. At this time, the first chip to power on and initiate the workflow, although operational for a very short time, performs an indispensable critical function. This chip will “declare” its identity to the device BIOS/firmware and pass this information to the operating system. Subsequently, when keys need to be exchanged during the encryption/decryption process, this chip will provide the key and its unique ID to assure the device on the other end of the connection of its security. Of course, the actual situation is more complex, but the basic operational principle is as described. This also fully explains the fundamental reason why it is essential to ensure that the first chip in the link always remains in its initial state and is not tampered with: the entire sequence of security and encryption operations is based on it as the trust foundation.

This also explains why it is necessary to ensure the high security of firmware updates or modifications for the foundational chip; otherwise, the entire security chain would collapse. Since some core encryption algorithms and key exchange mechanisms are also stored in the foundational chip and will undergo necessary updates as algorithms evolve, the update process itself typically employs encryption technology, further emphasizing the high security requirements of this stage.

Integrating all functions onto a single chip is very challenging because this is not executed by the main processor but requires a small control chip operating in a low-power environment. This is precisely where Lattice Semiconductor’s MachXO5™-NX TDQ FPGA comes into play. This small package chip generates a unique device ID through technologies such as Device Identifier Composition Engine (DICE), Security Protocol and Data Model (SPDM), and is equipped with two independent flash memory modules to support firmware upgrades and secure boot. Additionally, this chip integrates both traditional encryption algorithms and post-quantum encryption algorithms, providing the flexibility to support both types of algorithms, meeting the bitstream and data security needs of different organizations when switching between the two algorithms. More importantly, the chip introduces a PQC-based encryption and verification mechanism to ensure that the critical key exchange process meets quantum security requirements, effectively resisting the threat of “harvest now, decrypt later” (HNDL) attacks.

Bob O’Donnell is the President and Chief Analyst of TECHnalysis Research, a market research firm that provides strategic consulting and market research services for the technology industry and professional finance sector.

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