Alibaba Announces Major News: RISC-V AI Chip Has Entered Trial Production? Nvidia is Alarmed

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Recently, it has been reported that Alibaba’s self-developed AI inference chip based on the RISC-V architecture has entered the trial production stage. If true, this marks an important step for China in achieving self-control in high-performance AI chips. As one of the core results of Alibaba’s $53.1 billion AI investment plan, this chip not only embodies the company’s ambitions in cloud computing and artificial intelligence but also reflects the strategic determination of Chinese technology companies in core hardware independent innovation.

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Introduction to Sipeed NanoKVM Pro

Sipeed NanoKVM Pro is a compact 4K IP-KVM (Keyboard-Video-Mouse switch) that supports BIOS-level remote management, suitable for remote power on/off, system installation, and secure batch management of servers and desktop PCs.

• Dual Version Design

• Desk Version: Features a 1.47″ LCD touchscreen and a thumbwheel, suitable for desktop operation experience.

• ATX Version: Designed for installation inside a chassis or rack.

• Core Hardware Configuration:

• SoC: Axera Tech AX630C (Dual-core ARM Cortex-A53 @1.2 GHz)

• NPU: Supports up to 12.8 TOPS (INT4)/3.2 TOPS (INT8)

• Memory and Storage: 1 GB LPDDR4X + 32 GB eMMC

• Video and Network:

• Supports HDMI video capture: up to 4K@45fps, with future unlocks for 2K@95fps, 1080p@144fps, and other high frame rate modes.

• HDMI loop-through function + ultra-low latency (only 50–100 ms)

• Network connection: Gigabit wired Ethernet, Wi-Fi 6 (optional) and PoE (optional)

• Highlight of Expansion Features:

• Supports both NanoKVM and PiKVM open-source firmware, allowing flexible switching to meet different needs.

• Additional features include customizable touch display, LED sync light bars, multi-node batch management, AI smart assistant, etc.

Original link: https://www.cnx-software.com/2025/08/29/sipeed-nanokvm-pro-a-4k-ip-kvm-with-atx-and-desk-versions-pikvm-nanokvm-firmware-support/

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Goodbye EVM, Embrace RISC-V: Ethereum Reconstruction Centered on ZK

Core Viewpoints

• According to an article from Chain Catcher, Ethereum is heading towards the most significant “execution layer” reconstruction since its launch:Transitioning from EVM to RISC-V. The roadmap consists of three steps: first, replacing high-risk/high-complexity precompiles with RISC-V; secondly, coexistence of EVM and RISC-V VMs with mutual interoperability; finally, running EVM as a “simulated contract” (Rosetta) on RISC-V to maintain compatibility and verifiability.

• Technical internal factors driving the migration:In the era of ZK proofs, the “interpreter overhead” of EVM has become a bottleneck. Currently, zkEVM essentially proves the execution of the “EVM interpreter compiled into RISC-V”; an additional layer of interpretation leads to 50–800× performance loss; if directly targeting RISC-V, it is expected to achievenearly a hundred times improvement in execution efficiency, moving towards a Gigagas L1 with thousands of TPS.

Ecological Impact

• ZK Rollup Gains the Most: The vast majority of zkVMs have converged on RISC-V, and L1 and L2 “speak the same language”, significantly simplifying the stack and reusing compilation/verification tools; Optimistic Rollup needs to reconstruct fraud proofs or weaken coupling with Ethereum’s security.

• Developer and User Benefits: With the help of the LLVM ecosystem, mainstream languages like Rust/C++/Go can be used directly; proof costs are expected todecrease by about a hundred times, benefiting L1/L2 transaction fees simultaneously.

Security and Governance

• RISC-V hasSAIL formal specifications and hardware boundaries with privilege levels/ECALL, which is beneficial for verifiable kernels and clearer trust anchors; however, new risks that need to be faced include Gas metering model design, compiler supply chain security, and reproducible builds, with the community inclined to unify on RV64GC + Linux compatible ABI to avoid fragmentation.

Original link: https://www.chaincatcher.com/en/article/2202010

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Cuzco: Moving “Scheduling” to the Frontend with RISC-V High-Performance Core

Condor’s Cuzco, launched at Hot Chips 2025, is an 8-wide OoO core aimed at the high-performance licensable market. It simplifies backend dynamic scheduling by performing “time-based scheduling” (Time Resource Matrix, looking ahead 256 cycles, window 8 cycles) during the rename/allocate phase, relying on replay to handle variable latencies, thus achieving a new balance in power consumption and implementation complexity. This design is software transparent and can adjust slices and caches according to on-chip system requirements, but the throughput loss caused by replay and whether it can attract mass production customers remain key factors for its success.

Technical Interpretation

• Trade-off Philosophy: Cuzco reduces scheduling hardware probing overhead by “moving complexity from the backend to rename/allocate”, suitable for markets that require high single-thread performance while being constrained by power/area (like licensable cores for OEMs).

• Actual Costs: Time prediction-induced replay will consume execution resources, but the author believes the average replay rate is acceptable (if replay is excessive, it will erode profits); additionally, TRM assumes L1D hits, and workloads with significant memory latency will rely more on replay strategies.

• Market and Risks: As a licensable core, the biggest challenge is whether it can find large customers for mass production (the licensing market risk outside of hyperscalers still exists); however, in the high-performance segment comparable to SiFive P870 and Veyron V1, Cuzco’s configurability and energy efficiency/complexity trade-offs are selling points.

Original link: https://chipsandcheese.com/p/condors-cuzco-risc-v-core-at-hot

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Reports Indicate Alibaba’s RISC-V AI Acceleration Chip Has Entered Trial Production

Recently, Alibaba announced plans to invest at least 380 billion yuan (approximately $53.1 billion) in AI infrastructure over the next three years and develop AI inference chips based on the RISC-V architecture to reduce dependence on American technology. Following the announcement of the AI chip plan, its stock price rose by 12.9%, while Nvidia’s stock price fell by over 3%, reflecting market expectations for Alibaba’s expansion in the Chinese AI market share.

According to a report by Reuters (transferred from The Wall Street Journal), Alibaba is currently testing a new AI inference chip with stronger versatility, capable of covering a wider range of AI inference application scenarios. Unlike previous reliance on TSMC for manufacturing, this chip will be produced by domestic manufacturers, marking a significant milestone in the localization of AI chips.

This chip is currently in the testing phase, and specific details regarding architecture, process nodes, and performance metrics have not yet been disclosed. However, its development indicates that Alibaba is actively laying out a domestic RISC-V + AI inference technology path, building a diversified and self-controlled application ecosystem.

“Alibaba’s AI chip will be manufactured by domestic foundries, rather than the previously relied-upon TSMC. There is widespread speculation that the partner may be Semiconductor Manufacturing International Corporation (SMIC), but this has not been officially confirmed.”

#Extended Reading# Alibaba Denies Ordering 150,000 Cambricon GPUs, Is the Market Just Hearing Rumors? Market rumors suggested that Alibaba Cloud was making large-scale purchases of Cambricon AI GPUs, triggering a strong market reaction; however, Alibaba quickly refuted the claim, stating: “We did not place such a large order.” Subsequently, Cambricon’s stock price fell, and investor confidence was somewhat impacted. In the short term, such unconfirmed news remains a sensitive factor affecting the valuation of domestic chip companies.

Original link: https://www.reuters.com/world/china/chinas-alibaba-develops-new-ai-chip-help-fill-nvidia-void-wsj-reports-2025-08-29

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Review of the Latest Developments in RVA23 in China

RVA23 (RISC-V Architecture Profile 2023) is an important standard for the RISC-V architecture in the field of high-performance general-purpose processors, aimed at enhancing software compatibility and cross-platform capabilities. Since its approval by the RISC-V International Foundation in October 2024, significant progress has been made domestically in IP, hardware, distributions, and toolchains.

IP and Hardware: Accelerating Localization Process

Many domestic companies have launched high-performance RISC-V processor IPs that comply with the RVA23 standard. For example, the UX1030H processor launched by ChipRise fully supports virtualization, vector computing extensions, and IOMMU functions, targeting high-security and high-scalability application scenarios. Additionally, Alibaba Damo Academy’s Xuantie C930 processor has also been released, supporting Hypervisor virtualization and CoVE security framework, providing a solid foundation for the development of high-performance and AI scenarios.

Toolchains and Software Ecosystem: Gradually Improving

Domestic progress has been made in the construction of RVA23-related toolchains and software ecosystems. For instance, Alibaba Damo Academy has launched the Xuantie SDK for Linux, Android, and RTOS, integrating virtualization, security frameworks, and AI operator libraries, assisting RISC-V development in high-performance and AI scenarios.

Distributions and Operating Systems: Support Gradually Following

Mainstream operating systems are gradually advancing support for RVA23. For example, Ubuntu plans to update the admission threshold for RISC-V processors from the previous RVA20 profile to the latest RVA23 standard in its 25.10 version. Additionally, openEuler has also released an enhanced extended version based on RVA23, targeting servers, cloud, edge computing, and embedded scenarios, continuously providing more new features and functional expansions to serve more developers and users.

Ongoing Challenges and Future Outlook

Despite significant progress in domestic RVA23-related fields, some challenges remain. For instance, the adaptation of operating systems and the improvement of toolchains still need further advancement. However, with the promotion of the RVA23 standard and the continuous efforts of domestic enterprises, it is expected that the application of RISC-V in the field of high-performance general-purpose processors will further expand, promoting the realization of localization and self-control goals in the industrial chain.

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