The following is a comprehensive technical solution for hardware engineers to achieve Signal Integrity (SI), Power Integrity (PI), and EMC protection in PCB design, presented in a combination of tables and text:
1. Signal Integrity (SI) Design Specifications
1. Layout and Routing Optimization
Impedance Matching: Ensure that the characteristic impedance of transmission lines (such as 50Ω/75Ω) matches the impedance of the signal source/load to avoid reflections. In four-layer board designs, prioritize using microstrip or stripline structures, adjusting line width and dielectric thickness to achieve impedance control.
Differential Signal Design: For high-speed signals (such as clock, USB, HDMI), use differential pair routing, maintaining consistent line width and spacing, and avoiding vias and right-angle bends. The length error of differential pairs should be controlled within ±10 mils to suppress common-mode noise.
Reference Plane Continuity: High-speed signal paths must be closely adjacent to a continuous ground plane or power plane throughout, avoiding segmentation that leads to impedance discontinuities. When segmenting ground planes, use a “single-point connection” strategy and reduce the impedance of the segmented area through an array of vias (≥4 vias).
2. Crosstalk and Reflection Suppression
Spacing Control: The spacing between adjacent signal lines should be ≥3 times the line width (for example, a 6 mil line width requires an 18 mil spacing), with critical signal lines (such as DDR, SerDes) using orthogonal routing or shielded layer isolation.
Termination Matching: For long lines (length > 1/10 of the signal wavelength), add termination resistors (such as a series 33Ω) to absorb reflected wave energy. Differential signals use AC termination matching (such as a parallel 100pF capacitor).
Layer Stack Design: A typical four-layer stack is “signal-ground-power-signal”, with the dielectric layer thickness ratio controlled at 1:2 (for example, 0.2mm ground plane/0.4mm dielectric), reducing transmission delay.
3. Simulation and Testing Validation
Time/Frequency Domain Joint Analysis: Use HyperLynx or SI9000 for eye diagram simulation (eye height ≥10% of amplitude), rise time testing (target ≤0.1ns), and detect impedance fluctuations through TDR (Time Domain Reflectometry).
Actual Testing: Connect critical signal points to an oscilloscope (bandwidth ≥5GHz), overlay 10 cycles of the signal to generate an eye diagram, requiring an opening ≥80%.
2. Power Integrity (PI) Optimization
1. Power Layer Design
1.1 Low Impedance Distribution Network (PDN): The power layer of a four-layer board is divided in a “grid” pattern, with adjacent power areas connected by ≥8 mil vias (spacing 50 mil), controlling impedance within 5mΩ.
1.2 Decoupling Capacitor Matrix: Layered layout based on the “proximity distribution” principle:
(1) High-frequency decoupling: 0.1μF MLCC (X7R dielectric, self-resonant frequency ≥1GHz) placed next to chip power pins in 0402 package.
(2) Mid-frequency decoupling: Add 1μF ceramic capacitors (0603 package) to each IC power area.
(3) Low-frequency energy storage: Configure a combination of 10μF electrolytic capacitor + 0.1μF ceramic capacitor at the board-level power entry.
2. Noise Suppression Techniques
Power Segmentation Isolation: Isolate analog/digital power areas using ferrite beads (such as 0805 package 600Ω@100MHz), with digital ground and analog ground connected at a single point (Bypass capacitor bridging).
Switching Supply Noise (SSN) Management: In multi-chip systems, use “power noise clamping” technology, paralleling RC networks (such as 10Ω + 0.01μF) between critical IC power pins.
3. Thermal and Power Consumption Control
Current Density Limitation: Copper thickness of 1oz (35μm) has a carrying capacity of ≤1A/mm², with high current paths (such as CPU power supply) using 2oz + inner layer copper + thermal vias (via diameter 0.3mm, spacing 0.5mm).
Temperature Monitoring: Place thermistors near high-power devices (such as MOSFETs) to achieve thermal conduction through PCB copper (area ≥10mm²).
3. EMC Protection System Construction
1. Grounding System Design
Multi-layer Grounding Strategy:
Digital Ground: Covers all logic circuits, using star grounding (ground resistance <2Ω).
Analog Ground: Independent area, connected to digital ground at a single point through a 0Ω resistor (0805 package).
Shielding Ground: The metal shell achieves potential balancing through multi-point grounding (one grounding point every 50mm).
2. Shielding and Filtering
2.1 Metallization Treatment: In high-frequency areas (such as RF modules), use embedded shielding frames (thickness ≥0.5mm), filling seams with conductive glue (such as Eccosorb F63).
2.2 Filtering Network:
Differential Mode Filtering: Configure a π-type filter at the power entry (L=100nH, C=10μF + 0.1μF).
Common Mode Filtering: Connect common mode chokes (such as Bourns 3430 series) at the ends of differential signal lines.
3. Radiation Control
Antenna Effect Suppression:
Microstrip Line Termination: All unterminated signal lines should be <λ/8 in length (for example, a 1GHz signal line should be <15mm).
Edge Treatment: Leave a 3mm no-routing zone around the edges of the PCB to avoid edge routing forming dipoles.
4. Structural Reinforcement Design
4.1 Lamination Parameter Optimization: Use Rogers 4350B material (dielectric constant 3.48, Df=0.0037) in high-speed areas, and FR-4 (dielectric constant 4.2) in regular areas.
4.2 Mechanical Reinforcement: For long boards (>200mm), add intermediate support columns (epoxy resin + fiberglass), controlling deflection within 0.1mm.
It is recommended to combine specific project requirements with the four-layer PCB design secrets and high-speed PCB simulation guidelines for in-depth practice.