01. How many MMUs are there in a large system?
02. How many Translation regimes are there in an ARM Core?
03. What are the differences among EL1&0 Translation regime Stage 2, EL2 Translation regime Stage 1, and EL2&0 Translation regime Stage 1?
04. What is special about the TTBR1EL2 register, and who uses this register?
05. Is there a TTBR1EL3 register? Why?
06. What is a memory-map? How many sets of physical address spaces are there in an ARM system?
07. How many levels does the page table have? What is the minimum number of levels the page table can have? What is the maximum number of levels?
08. How large is the page table? Where is the page table stored? Who manages the page table?
09. Can the page table be placed in cache?
10. What is a Translation Table walk? What is a TLB?
11. Please briefly describe the process of page table lookup.
12. In a large system, how many bits is the physical address? What does the number of bits in the physical address refer to? How many bits is the virtual address? Who determines the number of bits in both the physical and virtual addresses?
13. Please explain the origin of the four terms: entry, descriptor, page table entry, and item.
14. There are cache attributes and share attributes in TCR, and there are also cache attributes and share attributes in the page table entry. What is the difference between these two?
15. Please briefly describe the concepts and significance of TTBR0 and TTBR1.
16. Please briefly describe the meanings of cacheability and shareability attributes.
17. What is the difference between stage 1 and stage 2?
18. There are many duplicate attributes in the descriptors of stage 1 and stage 2. What happens when the attributes conflict?
19. There are also some common attributes in the descriptors of L1, L2, and L2. What to do when there are duplicates?
20. What are the formats of descriptors?
21. What types of descriptors are there?
22. Briefly describe how shareability and cacheability are generally configured in the system software (operating system or hypervisor) you have observed.
23. What are the steps to enable an MMU?
24. What is a flat map? What is a full level table?
25. What are the AF and DBM attribute bits in the page table used for?
26. What is the nG attribute bit in the page table used for?
27. What is the Contiguous attribute bit in the page table used for?
28. What considerations are there at the moment the MMU is enabled?
These are some deep thinking questions. I currently cannot write answers one by one. Stay tuned, I will provide audio or video responses later.