FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?

The Verilog implementation of bidirectional ports provided in the resource package is as follows:FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?The synthesized schematic is as follows:FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?The original author’s IIC driver implementation of bidirectional ports is as follows, which is also a common practice in our actual work:FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?The synthesized schematic is as follows:FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?The schematics generated from both implementations are the same, with version 2018.3, and the results on the board are also identical.Therefore, can we conclude based on the opinions of some friends that: as long as the synthesized results are the same, it doesn’t matter how Verilog is written?Is this conclusion universally applicable? In other words, if we change the synthesis tool, can we ensure that the above conclusion remains valid?Expanding further, does the boundary of our design experience depend on the tool or the person themselves?Is it a logical error to use synthesis tools to deduce the correctness of syntax theory? Which came first, the syntax or the synthesis tool?In the previous session, a discussion arose regarding whether an initial begin can be synthesized, leading to many students debating. At that time, some students believed that the final results were the same, thus concluding that:initial begin can be synthesized.However, the Verilog syntax clearly states:initial begin cannot be synthesized.This is quite interesting and worth pondering. As AI develops, people will increasingly rely on tools, making it crucial to correctly understand the relationship between tools and humans.

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