Source: Learning About Things
Original Author: Xiao Chen Po Po
This article introduces the five typical failure modes in chip packaging: gold wire displacement, chip cracking, interface cracking, substrate cracking, and reflow soldering defects.
In the field of integrated circuit packaging failure analysis, gold wire displacement, chip cracking, interface cracking, substrate cracking, and reflow soldering defects are five typical failure modes. Their formation mechanisms are closely related to process control and require systematic optimization in conjunction with material properties and process parameters.
1. Gold Wire Displacement
Taking gold wire displacement as an example, this failure often originates from the drag force generated by resin flow during the packaging process. When the resin viscosity is too high or the flow rate is too fast, the gold wire can undergo irreversible displacement due to fluid shear forces, leading to contact between adjacent gold wires and causing short circuits, or even breaking due to excessive displacement. It is noteworthy that with the development of multi-pin ICs, the increased density of gold wires exacerbates the risk of displacement, necessitating the optimization of resin formulations, control of mold flow balance, and reduction of filler particle sizes (e.g., adjusting 2.5-250μm particles to smaller diameters) to reduce stress concentration.
2. Chip Cracking
Chip cracking is directly related to the brittle nature of single crystal silicon. Its failure may be hidden in stress processes such as wafer thinning, cutting, mounting, and bonding. Since initial cracks may not significantly affect electrical performance, high and low-temperature thermal cycling tests are required to accelerate crack propagation. The thermal stress caused by differences in thermal expansion coefficients of different materials can promote micro-cracks to expand to visible levels, ultimately affecting device reliability. The industry is currently exploring low-stress processes such as laser cutting and chemical mechanical polishing (CMP), as well as new technologies to enhance the mechanical strength of wafers through ion implantation, to reduce process damage.
3. Interface Cracking
Interface cracking often occurs at the junctions of dissimilar materials, such as the gold wire-pad interface or the plastic package-chip interface. Early failures may only manifest as intact electrical connections, but over time, thermal stress and electrochemical corrosion can gradually expand the cracks, leading to connection failures. This type of failure requires attention to the distribution of packaging stress and control of material purity, such as using low-stress epoxy molding compounds, optimizing solder ball alloy compositions to reduce interface stress concentration, and introducing in-situ X-ray inspection or acoustic scanning microscopy (C-SAM) for early non-destructive testing.
4. Substrate Cracking
Substrate cracking is commonly seen in flip-chip and wire bonding processes. Its causes involve defects in the chip/substrate itself and mismatches in soldering parameters (such as bonding force, temperature, and ultrasonic power). Such failures can lead to open circuits or high impedance, requiring the optimization of solder ball layouts, the use of high-reliability substrate materials (such as low CTE ceramic substrates), and precise control of soldering curves to prevent issues. Recent industry trends show that stress buffer layers are being introduced in through-silicon vias (TSV) and reconstituted wafer (RDL) processes in 3D packaging technology to reduce thermal-mechanical stress damage to substrates. Additionally, AI-driven process parameter optimization systems have achieved real-time monitoring and automatic adjustments, significantly improving yield rates.
5. Reflow Soldering Defects
In integrated circuit packaging processes, precise prevention and control of reflow soldering defects is a core aspect of ensuring high-reliability electronic manufacturing. Its failure modes involve warping, solder balls, voids, and other multidimensional issues, requiring systematic optimization in conjunction with material properties, process parameters, and intelligent detection technologies.
1）Warping
Warping is an internal stress release mechanism caused by differences in thermal expansion coefficients of dissimilar materials. During the thermal cycling of reflow soldering, mismatches in thermal expansion coefficients between the chip, substrate, and solder paste can lead to non-uniform deformation of the package, resulting in warping. The industry has currently achieved warping suppression through multi-parameter collaborative optimization, such as using low CTE composite substrate materials, dynamically adjusting the slope of the preheating-reflow-cooling curve, and introducing laser 3D measurement systems for real-time monitoring of warping. Notably, AI-driven adaptive process parameter systems are gradually being applied in high-end packaging production lines, using machine learning models to predict optimal temperature curves and controlling warping to within 50μm.
2）Solder Ball Defects
Solder ball defects are often seen in package-on-package (PoP) components, and their causes are closely related to stencil printing accuracy, solder paste wettability, and process environment control. Recent industry practices indicate that using laser-cut steel stencils combined with nano-coating technology can significantly improve stencil opening accuracy, controlling solder paste printing offsets to within ±25μm. Additionally, optimizing solder paste formulations to reduce surface tension, combined with nitrogen-protected reflow soldering processes, can reduce the probability of solder ball formation. For solder ball issues caused by moisture absorption, new intelligent solder paste management systems have achieved full-process temperature and humidity monitoring from refrigeration to use, along with vacuum stirring devices to ensure solder paste uniformity, effectively avoiding solder ball defects caused by moisture evaporation.
3）Void Defects
The formation mechanism of void defects is more complex, involving solder paste metal powder oxidation, process environment impurities intrusion, and temperature rise rate control among multiple dimensions. The industry is currently promoting a combination of high-purity oxygen-free solder paste and vacuum reflow soldering processes, reducing the oxygen content in solder paste to below 50ppm and controlling the void rate to within 3% through a stepwise temperature rise strategy. Furthermore, the deep integration of X-ray 3D imaging technology and acoustic scanning microscopy (C-SAM) has enabled non-destructive testing of internal defects in solder joints, combined with AI defect recognition algorithms to accurately locate voids, cracks, and other hidden failures, pushing packaging yield rates above 99.9%.
In addition to the typical defects mentioned above, issues such as incomplete solder paste melting, poor wetting, and bridging also require close attention. By optimizing the surface treatment process of pads, using electroless nickel immersion gold (ENIG) or organic solderability preservative (OSP) coatings to enhance solderability, and combining intelligent printing equipment for precise solder paste application, the risk of bridging caused by excessive solder can be avoided. In terms of preventing cold solder, solder wire, and other defects, the industry is exploring the combined application of low-temperature solder alloy systems and rapid cooling processes to enhance mechanical strength and electrical reliability by controlling solder joint grain structures.
As the demands for high-density packaging increase with 5G and AI chips, reflow soldering processes will evolve towards intelligence and sustainability. The deep integration of intelligent temperature control systems and digital twin technology can achieve real-time optimization of process parameters and defect prediction. The development and application of nano-material solder pastes and biodegradable fluxes will promote the transformation of packaging processes towards environmental friendliness. By establishing a comprehensive quality control system from material selection, process design to intelligent detection, the industry is gradually achieving a leap from passive failure analysis to proactive defect prevention, providing solid support for high-reliability electronic manufacturing.
END
The reproduced content only represents the author’s views
It does not represent the position of the Semiconductor Institute of the Chinese Academy of Sciences
Editor: Catnip
Chief Editor: Yuzu Lu
Submission Email: [email protected]
Previous Recommendations
1. Interaction between Radiation and Semiconductor Materials
2. Understanding Chip Failure Analysis in One Article
3. Classification of Semiconductor Materials
4. Technical Challenges of HBM in Advanced Packaging
5. Semiconductor and CMOS Processes
6. The “Film” of Photolithography: Masks in Chip Manufacturing
