Programming and Reading Demura Data in AMOLED Display Driver Chip
YANG Guozhong, ZHANG Jie, CHEN Jie
Abstract — The Demura data to be used in the driver chip of AMOLED display need to be saved in the non-volatile memory outside the driver chip. After the driver chip is powered on, the data should be read from the non-volatile memory back to the SRAM in the driver chip for display image correction. In this paper, SPI MASTER and related interface module are designed to achieve two main functions: one is to automatically burn Demura data into SPI Flash; secondly, after the driver chip is powered on, Demura data in SPI Flash will be automatically read into the SRAM in the driver chip. The SPI MASTER in this paper supports the Quad SPI with a data throughput four times that of the Standard SPI.
Index Terms — integrated circuit design, display driver, data reading.
1 Introduction
The term Mura originates from Japan, originally meaning uneven brightness, but has been extended to refer to the visual perception of different degrees of color variation in the same color image on a display panel. Due to the limitations of the process, AMOLED may also exhibit Mura phenomena, thus compensation methods are needed to eliminate Mura as much as possible. There are two methods for Mura compensation: internal compensation and external compensation. The Mura compensation method discussed in this paper, namely Demura, refers to the external compensation method. The general process of this method is as follows: first, a high-resolution and high-precision CCD camera is used to capture the lit AMOLED panel; then, based on the data collected by the CCD camera, the pixel color distribution characteristics are analyzed, and Mura is identified according to the corresponding algorithm. After obtaining the Mura data and the corresponding Demura compensation algorithm, Demura data is generated; finally, the Demura data is burned into a memory, such as SPI Flash, and a re-photograph of the image after Demura data compensation is taken to confirm that Mura has been eliminated.
The SPI MASTER and the interface module between DSI Rx and Demura SRAM designed in this paper automatically burn the Demura data into SPI Flash and read data from SPI Flash into Demura SRAM for use by the Demura compensation algorithm circuit.
2 Technical Analysis
2.1 AMOLED Technology
AMOLED (Active-matrix organic light-emitting diode) is a display technology. OLED (organic light-emitting diode) describes a specific type of thin-film display technology that is organic electroluminescent display; AM (active matrix) refers to the pixel addressing technology behind it.
Compared to LCD (liquid crystal display) technology, AMOLED technology has advantages such as deeper blacks, wider color gamut, higher contrast, thinner profile, lower power consumption, and greater flexibility, making it increasingly popular in handheld electronic products such as mobile phones, smartwatches, and tablets.
2.2 MIPI-DSI Technology
MIPI (Mobile Industry Processor Interface) is an open standard and specification initiated by the MIPI Alliance for mobile application processors. MIPI-DSI (MIPI-Display Serial Interface) is a solution specifically provided by the MIPI Alliance for the displays of mobile devices.
2.3 SPI Protocol
2.3.1 Standard SPI
SPI (Serial Peripheral Interface) is a serial communication protocol originally defined by Motorola on its MC68HCXX series processors. It is a high-speed, full-duplex, synchronous communication bus. The communication principle of SPI is simple; it operates in a master-slave mode, typically involving one master device and one or more slave devices, requiring at least four lines, although three lines can suffice in unidirectional communication. These four lines are SDO (data output), SDI (data input), CLK (clock), and CS (chip select). During each CLK cycle, SPI devices send and receive one bit of data, effectively exchanging one bit of data. This type of SPI is commonly referred to as Standard SPI.
2.3.2 Quad SPI
Quad SPI is specific to SPI Flash and does not apply to all SPI peripherals. For SPI Flash, full-duplex is not commonly used; thus, the usage of SDO and SDI in Standard SPI is extended to operate in half-duplex, and two additional I/O data lines are added to increase the data transfer bit width. Figure 1 shows a packaging diagram of a Quad SPI supported SPI Flash.
In this, DI is data input, DO is data output, /WP is write protect input, /HOLD is hold input (/RESET is reset input). During operation, the host can send a command byte to the Quad SPI supported Flash to command it to enter Quad Mode, thus DI becomes IO0 (In/Out 0), DO becomes IO1 (In/Out 1), /WP becomes IO2 (In/Out 2), and /HOLD becomes IO3 (In/Out 3). In this way, four bits of data can be sent or received in one clock cycle, which is four times the data transfer speed of Standard SPI, commonly referred to as Quad SPI.
3 System Block Diagram and Explanation
Figure 2 is the system block diagram for burning and reading Demura data.
3.1 System Overview
In the AMOLED display testing machine, the MIPI-DSI Transmitter (DSI Tx) sends Demura data to the MIPI-DSI Receiver (DSI Rx), which temporarily stores the data in Demura SRAM. Then, the SPI MASTER is activated, which automatically reads the Demura data from Demura SRAM into the SPI MASTER, and writes it to SPI Flash in Quad SPI mode, burning it. SPI Flash is programmed one page at a time, with each page containing 256 Bytes of data, and it takes approximately 1 ms to burn one page. The Demura data is relatively large, at least over 10 Mbit. It takes at least about 0.7 seconds to burn the entire Demura data (calculated at 15 Mbit). Since the testing machine’s testing time for the AMOLED display is counted in seconds, while the SPI MASTER automatically burns the SPI Flash, it can simultaneously test other parameters of the AMOLED display, saving valuable time for the testing machine.
After powering on the AMOLED display, the SPI MASTER automatically reads data from SPI Flash into the SPI MASTER in Quad SPI mode, composes the data for the width of Demura SRAM, and then writes it into Demura SRAM. The AMOLED display driver chip used in this paper employs a built-in oscillator clock (OSC clock) as the pixel clock, working in a manner that outputs three pixels per pixel clock. This design has a low frequency requirement for the OSC clock (it can be less than 70 MHz). After powering on the AMOLED display, it is necessary to immediately use Demura data to correct the display image, so the reading speed from SPI Flash must be as fast as possible. Since the highest frequency clock within the chip is the OSC clock, the working clock of the SPI MASTER and the clock accessing SPI Flash is also the OSC clock, while accessing SPI Flash in Quad SPI mode meets the reading time requirement (less than 100 ms). The SPI MASTER designed in this paper can support various manufacturers’ SPI Flash models based on different register configurations.
3.2 DSI Rx Writes to Demura SRAM
DSI Tx sends Demura data to DSI Rx in a long packet format. After receiving the data, DSI-Rx sends it to the DSI_DEMURA_INTF module. Since the data width sent by DSI-Rx to the DSI_DEMURA_INTF module is inconsistent with the width of Demura SRAM, and the previous data sent may not have been completely sent to SRAM, the DSI_DEMURA_INTF module first needs to concatenate the remaining data from the last send to SRAM, then package it into data of SRAM width, and store the tail number less than SRAM width for concatenation with the next batch of data sent from DSI-RX. Thus, the data sent to SRAM (DSI_DM_FFI) is prepared. The address (DSI_DM_ADDR) is the last sent address + 1, then together with the write enable signal (DSI_DM_WENB), chip select signal (DSI_DM_CEB), and MUX select signal (DSI_DM_SEL), it is sent to the SRAM MUX. After selection by SRAM MUX, the Demura data can be written to SRAM.
3.3 DSI Rx Reads from Demura SRAM
DSI Tx reads the data from Demura SRAM and compares it with the data written to Demura SRAM by DSI Tx to verify whether the logical path from DSI Rx to Demura SRAM is correct and whether the data burned in SPI Flash is correct. DSI Tx first configures the maximum data amount (in Bytes) to be read for one read operation to DSI Rx. Then, DSI Rx sends the read start signal (DSI_RD_START) and data enable signal (DSI_RD_EN) to the DSI_DEMURA_INTF module. Upon receiving this, the DSI_DEMURA_INTF module begins reading data from Demura SRAM and caches the read data. It then sends one Byte of the cached data to DSI Rx, along with the actual data amount for this read operation (in Bytes, and less than the previously configured maximum data amount) for use when DSI Rx forms the DSI packet. After sending one Byte of data to DSI Tx, DSI Rx sends the continue read signal (DSI_RD_INC) to the DSI_DEMURA_INTF module, which then sends another Byte of data to DSI Rx. This process repeats until the actual data amount for this read operation is completely sent.
3.4 SPI MASTER
Once DSI Rx has written all Demura data to Demura SRAM, the testing machine sends the corresponding command to start the SPI MASTER burning SPI Flash process. First, the SPI MASTER sends the address (SPI_DM_ADDR), write enable signal (SPI_DM_WENB), chip select signal (SPI_DM_CEB), and MUX select signal (SPI_DM_SEL) to the SRAM MUX. After selection by SRAM MUX, the Demura data (SPI_DM_FFO) can be transferred from Demura SRAM to SPI MASTER. Then, the SPI MASTER writes the 256 Bytes (one page) of data to SPI Flash in Quad SPI mode and burns it. This process is repeated until all Demura data is burned into SPI Flash.
The system reset signal of the driver chip triggers the SPI MASTER to read from SPI Flash. First, the SPI MASTER receives data from SPI Flash in Quad SPI mode at a rate of 4 bits per clock, composes it into 8-bit data, and caches it. Then, the SPI MASTER packages the cached data into data of Demura SRAM width and sends it along with the address (SPI_DM_ADDR) which is the last sent address plus 1, together with the read/write enable signal, chip select signal, and MUX select signal to the SRAM MUX. After selection by SRAM MUX, the data read from SPI Flash can be written to Demura SRAM.
The connections between the SPI MASTER and SPI Flash are as follows: the chip select signal CSB of the SPI MASTER is connected to the /CS of SPI Flash, which is active low. The clock output of the SPI MASTER is SCLK, connected to the CLK pin of SPI Flash. In Standard SPI mode, the data output of the SPI MASTER (called MOSI), which is the master device’s data output and the slave device’s data input, is connected to the data input pin DI of SPI Flash. The data input of the SPI MASTER (called MISO), which is the master device’s data input and the slave device’s data output, is connected to the data output pin DO of SPI Flash. The SPI MASTER outputs /WP (write protection function) and /HOLD (pause function), which are connected to the /WP and /HOLD pins of SPI Flash, respectively. In Quad SPI mode, MOSI, MISO, /WP, and /HOLD all become bidirectional I/O data lines, corresponding to IO0, IO1, IO2, and IO3.
3.4.1 SPI MASTER Burns SPI Flash
The SPI Flash that supports Quad SPI has a non-volatile bit called QE (Quad Enable) in its status register. This bit’s default value is usually 0, and only by setting this bit to 1 can Quad SPI operations be performed on SPI Flash. During the entire burning process, the SPI MASTER performs the following operations (taking Winbond W25Q16FW as an example, viewed from the pins of SPI Flash).
(1) Write the Write Enable (WREN) command (taking SPI mode 0 as an example). The clock used internally by the SPI MASTER and the CLK sent to SPI Flash are of the same frequency and phase. The difference is that the internal clock is free running, while the CLK sent to SPI Flash is only present during data transmission and stops immediately after data transmission ends. Before the first rising edge of CLK, that is, when /CS is pulled low, the SPI MASTER has already placed the highest bit of WREN onto MOSI using the internal clock. When the first rising edge of CLK arrives, SPI Flash can start receiving data. Then, on the falling edge of CLK, the SPI MASTER continues to output the WREN command in order from the highest bit to the lowest bit. After sending 8 bits of data, CLK returns to 0, and /CS is pulled high, ending the writing of the WREN command. Figure 3 shows the process of writing the WREN command.
(2) Read the status register and check whether the Write Enable Latch (WEL) is 1. If it is not 1, repeat the first command. The WEL bit of Winbond W25Q16FW is in its status register 1 at bit 1, and the corresponding read status register command is 0x05. As shown in Figure 4, after reading 8 bits of the status register, as long as /CS is not pulled high, SPI Flash will continuously output the corresponding 8 bits of status register value. This function is very effective for checking whether the burning process has completed.
(3) Write the Write Status Register (WRSR) command, setting the QE bit to 1. The QE bit of Winbond W25Q16FW is in its status register 2 at bit 1, and the corresponding WRSR command is 0x31. Figure 5 shows the WRSR command.
(4) Repeat the read status register command in step 2 to check whether the QE bit has been set to 1. If the QE bit is not set to 1, repeat steps 1, 2, and 3. If the QE bit has been set to 1, the Quad SPI mode of SPI Flash has been successfully configured, and data can be read and written in Quad SPI mode. Since the QE bit is non-volatile, even if the SPI Flash loses power and restarts, the QE bit will still be 1 and does not need to be reset. Additionally, although the SPI Flash is already in Quad SPI mode, it still supports Standard SPI, and the SPI MASTER can still read and write data in SPI Flash using Standard SPI mode.
(5) Send the Quad page program command (0x32) in Standard SPI mode, along with the 24-bit address where the data is stored in SPI Flash (based on the last burned address + 256), then send 256 Bytes of data read from Demura SRAM using IO0, IO1, IO2, and IO3 in a manner that writes 4 bits of data per clock. Figure 6 shows the Quad page program command.
(6) Execute step 2 to poll the status register, checking the BUSY bit (Write In Progress) to see if it is 0. The BUSY bit of Winbond W25Q16FW is in its status register 1 at bit 0. If this bit is 1, it indicates that SPI Flash is currently burning. Once this bit is queried to be 0, it indicates that the burning is complete, and the next page can be burned.
(7) Repeat steps 5 and 6 until all Demura data is burned into SPI Flash. The SPI MASTER sends a burning end signal to the register for the testing machine to query.
3.4.2 SPI MASTER Reads SPI Flash
After powering on the driver chip, the SPI MASTER automatically reads Demura data from SPI Flash in Quad SPI mode. During the entire read operation from SPI Flash, the SPI MASTER will perform the following operations.
(1) Read the status register, as in step 2 of the burning process, checking whether the QE bit has been set to 1. If the QE bit is 0, execute steps 1, 2, 3, and 4 of the burning process. If the QE bit is already 1, begin executing the following step 2.
(2) Send the Quad Output Fast Read command in Standard SPI mode, along with the 24-bit address. Wait for 8 dummy clocks; during this time, the SPI MASTER configures all 4 data I/Os as inputs while SPI Flash configures all 4 data I/Os as outputs. The SPI MASTER then begins to read the data from SPI Flash in a manner that receives 4 bits of data per clock from IO0, IO1, IO2, and IO3. Figure 7 shows the Quad Output Fast Read command.
(3) The data read from SPI Flash is composed into the width of Demura SRAM and written into Demura SRAM. A count is made for each Byte read. When the count equals the amount of Demura data, the SPI MASTER pulls /CS high and stops reading from SPI Flash.
4 Conclusion
This paper discusses the burning and reading of Demura data in the AMOLED display driver chip. The designed SPI MASTER reads data at a speed four times that of Standard SPI due to its use of Quad SPI, and supports multiple SPI Flash models aside from Winbond. Additionally, for new SPI Flash models, there is a manual configuration mode that can configure read/write status register commands, burn commands, etc., making it very flexible. The specific compensation algorithm for Demura data involves confidentiality issues and will not be elaborated on here.
Currently, the chip has successfully typeout, adopting UMC 40 nm technology, and has entered the laboratory testing phase. Tests have confirmed that the burning and reading operations of Demura data have been successful, and the reading speed meets the specifications (less than 100 ms).
References
[1] Liu Wenjiang. Research on Low Power AMOLED Pixel Circuit and Driving Methods [D]. Shanghai: Shanghai Jiao Tong University, 2014.
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