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Abstract: Before tape-out, it is necessary to check the layout, routing, drive/load, IO, and design rules of the chip. Based on years of tape-out experience, the necessary checks for each part are summarized as follows.
1. Layout Check
1) Consider the direction and position of the output pin before layout, try to keep the clock pin away from the analog signal pin;
2) Separate n-wells of different potentials, especially in mixed-signal circuits;
3) Add dummy resistors to improve the matching of resistors, and both ends of the dummy resistors should be grounded;
4) For circuits with high matching requirements for differential pairs, pay attention to the symmetry of the layout, using structures like cross fingers and dummy to enhance layout symmetry;
5) The gate orientation of MOS transistors in each module of the layout should be as consistent as possible, avoiding a mix of horizontal and vertical orientations;
6) Check whether the Tap Cell in the digital standard cells needs to be connected to power or ground;
7) Check for any missed connections to power or ground for Tie High and Tie Low Cells in the digital standard cells;
8) Add corresponding Pad Fillers on the digital and analog IO rings, add Core Fillers in the digital core, and then export the GDS file;
9) For ESD protection devices with a double cross-finger structure, place the source on both sides and the drain in the middle to facilitate even conduction of ESD current;
10) For multi-target tape-out, reserve at least 80µm (consult the packaging factory for specifics) of slot spacing between dies. Try to ensure that the die cutting can be done in one go in both horizontal and vertical directions (i.e., avoid interleaving the arrangement of chips);
11) For MPW tape-out, when determining the chip area, keep the total area slightly smaller than the specified size, and the shape of individual chips is best rectangular to facilitate MPW layout splicing.
2. Routing Check
1) Metal connections should not be too long; if long connections are unavoidable, add buffers in the middle to improve drive capability;
2) The width of long connections should not be too narrow;
3) Avoid routing metal connections over the channel of the transistors;
4) Ensure that connection junctions are drawn overlapping during layout to prevent open circuits that are hard to detect visually;
5) Digital circuit routing should not pass through analog circuit devices to avoid introducing strong interference that affects the normal operation of the analog circuit. Conversely, analog circuit routing should not pass through digital circuits;
6) In mixed-signal circuits, it is best to add Guard Rings around the analog circuit, and if necessary, use separate pins to ground or connect to power supply voltage for isolation;
7) For high-voltage circuits, to avoid tip discharge, use 135-degree angles at corners, and avoid 90-degree or acute angles;
8) Separate the power and ground lines inside the chip from those on the ESD; also separate the power and ground lines for digital and analog signals;
9) Important high-frequency signal lines must consider isolation. Generally, use metal ground lines of the same level to isolate on both sides. High-frequency clock lines should also be isolated with ground lines to prevent interference with other signals. Clock lines are best routed parallel to power and ground lines to minimize crossings, preventing parasitic capacitance from coupling to power and ground. The performance of high-frequency lines largely depends on the layout design.
3. Drive/Load Check
1) Check the current carrying capacity of the metal lines;
2) If space allows, the more vias and contacts, especially in the input/output sections, the better;
3) Check whether the drive capability of the analog output pins is sufficient. The equivalent capacitance of the pad can be used as a load to observe if the drive capability is enough;
4) Ensure sufficient distance between the contact of the Drain and the Poly for output transistors directly connected to IO, ideally greater than or equal to 1.5um (this value may vary with different processes), or add a SAB layer to promote current uniformity and ensure sufficient ESD reliability;
5) When the current is large (100mA), ensure that the distance between the PMOS and NMOS layouts directly connected to the IO is at least 30um to prevent latch-up.
4. IO Check
1) Do not place weak signal and strong signal analog IO inputs together, as weak signals will be interfered with by strong signals;
2) In mixed-signal circuits, separate power rings for digital IO and analog IO;
3) Check whether the IO power ring on the IO is correctly connected to power and ground;
4) For CMOS pairs directly connected to I/O, regardless of being input or output, the spacing (active area) between NMOS and PMOS should be significantly increased. For IO connected to the working voltage level inside the CORE, this spacing should be greater than 2 um (40 nm process); for IO connected to a voltage level higher than that inside the CORE, this spacing should be larger (e.g., greater than 3.2 um);
5) For GDS files with IO exported from automatic layout routing software (such as Astro or ICC), replace the IO in the layout with the IO from the complete IO GDS files provided by the Foundry (including Pad Filler) before importing into Virtuso for DRC to prevent extra layers like HTNWL;
6) Note that chip packaging is generally arranged in a counter-clockwise manner, and the arrangement order of chip IO should be consistent with the packaging pins;
7) The layout of chip IO PAD should not be symmetrically arranged up, down, left, and right to facilitate machine recognition during packaging (machines only recognize the PAD layout and do not recognize information inside the CORE), to prevent packaging errors due to failure to recognize.
5. Design Rule Check
1) The length and width of capacitors should not differ too much to ensure uniform electric field distribution on the upper and lower plates;
2) Add grounding holes in vacant spaces of the layout to avoid latch-up effects;
3) Pay attention to the antenna effect for large metal areas connected to the gate, and perform jumpers if necessary, ensuring an antenna effect check before final tape-out;
4) Functional simulation of digital circuits, simulation after layout and routing, and timing simulation must include IO and pass;
5) During SMIC tape-out, the process files cannot use those included in the PDK, and the latest files must be downloaded from the Technology file directory;
6) Before layout drawing, check the Foundry (e.g., SMIC) website for the latest DRC and LVS check files; if available, immediately adopt the new DRC and LVS files (DFM checks are needed after 65nm);
7) After digital-analog integration, re-import the exported GDS files back into Virtuso to check each layout level to prevent loss of levels and perform DRC and LVS checks;
8) If there are DRC violations in digital standard cells or other third-party IP, promptly communicate with the IP provider to ensure the functionality of the IP library is correct and can pass the latest DRC checks;
9) Each chip must have a LOGO. It is recommended that the LOGO consists of: chip name_tape-out date, e.g., ADC_080618;
After completing the above checks, back up the design data to avoid data loss. Below is an example of the considerations for filling out the tape-out form for the SMIC 0.18um MPW (Multi Project Wafer) process.
Example: SMIC 0.18 MPW Tape-Out Notes
1) PTO (Pre-tape Out) and FSR (Foundry Service Request) must be submitted before the tape-out time (deadline 1) provided on the SMIC NOW website; other documents can be submitted one week later (deadline 2). Once submitted, PTO is locked and cannot be modified. If changes are needed, contact CE;
2) Gate-OX Layers: Dual Gate indicates two thicknesses of gate 1.8/3.3V;
3) Digital IO will use dif resistors, which need to be added to the FSR form;
4) Polymide refers to the top layer of the chip being made of polymide for radiation protection, which is not needed for ordinary chips;
5) Seal Ring is located outside each chip (beyond the IO), acting as protection between the chip and the slot. If you choose to have SMIC add the Seal Ring, it can only be added to the outermost part of each MPW chip, not between each IP inside the MPW chip;
6) Wafer Type: Epitaxial wafer and non-epitaxial wafer. Epitaxial wafers are mainly used for high-power chips, while we choose Prime Wafer for ordinary chips;
7) Back Grinding Thickness is chosen based on the packaging factory’s requirements for the thickness of the bare chip;
8) SMIC directly completes cutting on the wafer, so each cut will go all the way through;
9) After FSR submission, Sales will send a quotation, and the PO must be filled out according to the quotation, signed and stamped, and sent back to Sales before deadline 2. Note that the Order items column in the PO must include MPW and information such as area and required die quantity;
10) The LDDI (Layout Design Database Information) form is generated based on the FSR.
Errors are mainly divided into two types
(1) Layers present in LDDI but not found in GDS;
(2) Layers found in GDS but not present in LDDI.
For the first type of error: confirm whether the layer is needed in the layout, if not needed, change the layer number to N/A;
For the second type of error: first check if there are errors in the FSR form. If the FSR is correct, you can add these layers in LDDI. Layer names and numbers can be found in the .tf or .map files.
The above experience summary is for reference by practitioners in China’s semiconductor industry.
Author: Han Yan: Professor at the College of Micro-Nano Electronics, Zhejiang University, Doctor of Engineering, Doctoral Supervisor. Formerly served as the director of the teaching and research office, deputy director of the research institute, deputy director of the Department of Information and Electronics, and deputy director of the management committee of the Hangzhou National High-Tech Industrial Development Zone (on-the-job). Council member of the IC branch of the China Semiconductor Industry Association, council member of the China Power Supply Society, executive council member of the Zhejiang Power Supply Society, council member of the Zhejiang Electronics Society. Engaged in teaching and research in microelectronics and integrated circuit design, power device design, undertaking more than 60 scientific research projects including the National 863 IC design major project, National Science and Technology major project (Nuclear High Base), National Natural Science Foundation general project, Ministry of Education doctoral fund, Ministry of Industry and Information Technology electronic information industry development fund project, major science and technology project in Zhejiang Province, Zhejiang Province Natural Science Foundation, overseas cooperation projects, major horizontal projects, and enterprise commissioned projects. Published eight monographs and two translations. Published 145 papers (including top international journals in microelectronics such as JSSC), and authorized 135 invention patents (including 3 US and Japanese patents).
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