First Tape-Out Success Rate at 14%, 1.4nm Process Costs Soar: Opportunities for Domestic EDA?

First Tape-Out Success Rate at 14%, 1.4nm Process Costs Soar: Opportunities for Domestic EDA?

As chip scales continue to expand and design complexity increases, the development of EDA software has not kept pace.

Recent statistics show that the first tape-out success rate for chips has hit a new low of only 14%. Previously, it was 28%, and even earlier it was 30%, showing a decline almost every year.

This undoubtedly indicates that EDA software has not yet met the design demands of increasingly complex chips.

Meanwhile, TSMC’s 1.4nm process costs are also skyrocketing. According to the latest reports, the cost per tape-out has reached as high as $45,000, a 50% increase from the previous generation’s most advanced 2nm process (approximately $30,000).

In my view, this is a signal—process technology is nearing its limits, costs are out of control, and growth is exponential.

It is well known that although the process node numbers seem to be continuously “advancing”, they are more of a numerical game. The so-called “advanced processes” today often involve minor optimizations on existing technologies, followed by a name change. Even so, costs remain difficult to suppress. The entire industry has entered a deep water zone, making progress challenging.

At the same time, Samsung, which once competed with TSMC, is gradually falling behind. Now, TSMC stands alone at the forefront, but how long can it sustain this position of carrying the banner of advanced processes? It is hard to predict.

On one side, design complexity is skyrocketing, and on the other, process technology is hitting its peak. For the EDA industry, this is both a challenge and a window of opportunity.The slowdown or even stagnation of process advancements means that the market landscape may be restructured, and the EDA industry is at a historical turning point.

Domestic EDA is seizing this opportunity. For example, companies like Hejian Technology have opened some tools for free use, aiming to quickly expand their market presence. This strategy is quite clever—first cultivate usage habits, and later gradually recover costs through commercialization.

In fact, when international EDA giants first entered the Chinese market, they did similar things. They collaborated with universities, offering free licenses while tacitly allowing the existence of piracy in the market. The goal was clear: first cultivate users and secure their position. Once chip companies grew stronger, they would return to charge fees, even retroactively collecting past dues.

This strategy was very effective, and currently, the global EDA market is firmly controlled by the three giants: Synopsys, Cadence, and Siemens EDA, which together hold 80% of the market.

In terms of supporting advanced processes, domestic manufacturers are also striving to catch up.

  • Gaon Electronics claims that its core technology supports advanced nodes such as 7nm, 5nm, 3nm, as well as transistor structures like FinFET, FD-SOI, GAA;
  • The Institute of Microelectronics of the Chinese Academy of Sciences has also supported physical verification for 28nm HKMG, and DFM tools have been purchased by Huawei HiSilicon and are undergoing domestic replacement verification at SMIC.

Although we still have a gap with the global top players, the good news is:the advancement of advanced processes is nearing its limits, and the catch-up of domestic EDA is not out of reach.

The decline in tape-out success rates indicates that the acceleration of chip design complexity is still ongoing, placing higher demands on EDA tools. This poses a significant challenge for the global EDA industry and represents a historic opportunity for domestic EDA.

How to better utilize AI is a key point that may enable a “leapfrog” advancement.

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