On June 5, semiconductor IP company Alphawave Semi announced that its UCIe IP subsystem has successfully taped out, utilizing TSMC’s 2nm (N2) process, supporting a 36G Die-to-Die data rate. This IP is fully integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.
This milestone builds on the recently launched Alphawave Semi AI platform, indicating readiness to support future disaggregated SoCs and vertically scalable infrastructure for large-scale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the first companies to achieve UCIe connectivity on 2nm technology, marking a significant step forward for the open chiplet ecosystem.
Mohit Gupta, Vice President and General Manager of Custom Chips and IP at Alphawave Semi, stated: “We are proud to lead the industry into the 2nm era with the first UCIe IP at this advanced node. Our 36G subsystem validates a new class of high-density, energy-efficient chiplet connections and paves the way for 64G UCIe and beyond, which is crucial for AI and high-density networking applications.”
Alphawave Semi is among the first in the industry to adopt TSMC’s 2nm process for its UCIe IP subsystem, offering 36G performance, 11.8 Tbps/mm bandwidth density, ultra-low power and latency, as well as advanced features such as real-time per-channel status monitoring and comprehensive testability. It complies with the UCIe 2.0 standard and supports multiple protocols, including PCIe®, CXL™, AXI, and CHI, utilizing Alphawave Semi’s highly configurable and efficient D2D controller.
Alphawave Semi is advancing key ecosystem collaborations to achieve breakthrough technologies, leveraging D2D-based open chiplet interoperability to drive a broader AI connectivity platform for the industry. The UCIe IP on TSMC’s 2nm process affirms its position as a leading proponent of a scalable, open chiplet ecosystem.
Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC, stated: “Our latest collaboration with Alphawave Semi highlights our mutual commitment to advancing high-performance computing through design solutions that fully leverage the performance and energy efficiency advantages of TSMC’s advanced processes and packaging technologies. This milestone demonstrates how our close collaboration with open innovation platform (OIP) partners like Alphawave Semi can rapidly deliver advanced interface IP and custom chip solutions to meet the growing demands of AI and cloud infrastructure.”
Alphawave Semi is executing its plans to deliver next-generation UCIe solutions, supporting 64G UCIe, enabling AI and HPC customers to stay ahead in the rapidly evolving chiplet-driven environment.
Editor: Lin Zi, Chip Intelligence
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