The core objective of chip architecture exploration is to find the optimal hardware architecture solution for specific workloads under given constraints of power consumption, performance, area, and cost. Traditional methods, which heavily rely on experience and simulation, are gradually being replaced by automated and intelligent methods based on big data and artificial intelligence.
1. Domestic Chip Design Architecture Exploration Methods
Domestic methods closely follow international trends, but due to certain gaps in EDA tools, advanced IP, and processes, they emphasize scenario-driven and rapid iteration, especially in fields like AI chips and edge computing.
1.1 Scenario and Demand-Driven Architecture Innovation
· “Software Defined Hardware”: For specific applications (such as AI inference, autonomous driving, intelligent security), the core algorithms and software stack are first analyzed, and then the hardware architecture is defined in reverse. For example, Cambricon’s MLU and T-head’s Xuantie CPU are deeply optimized for AI matrix operations and specific instruction sets.
· Heterogeneous Computing Integration: A heterogeneous architecture commonly adopts CPU + GPU/NPU + other accelerators. The focus of exploration is on how to efficiently integrate these IP cores and design low-latency, high-bandwidth on-chip interconnect networks.
1.2 Platforms Based on Advanced Simulation and Prototyping Verification
· High-Performance Simulation: A large number of tools from the three major international EDA vendors (Synopsys, Cadence, Siemens EDA) are used for RTL simulation, power analysis, and timing verification.
· FPGA Prototyping Verification: This is a crucial aspect heavily relied upon by domestic companies. By mapping designs onto large-scale FPGA boards, real software can be run early for hardware/software co-verification and optimization, significantly shortening the development cycle.
1.3 Learning from and Integrating Open Source Ecosystems
· The Rise of RISC-V Architecture: China is one of the most active participants in the RISC-V ecosystem. Exploring architecture based on the open-source RISC-V instruction set allows for freedom from licensing restrictions and focuses on microarchitecture innovation (such as Alibaba T-head’s C series cores).
· Open Source IP and EDA Tools: There is a growing attempt to use high-level hardware description languages like Chisel and SpinalHDL, as well as some open-source EDA toolchains, to lower the exploration threshold.
1.4 Preliminary Applications of AI-Assisted Design Methods
· Leading domestic chip companies and research institutions have begun to develop or introduce AI for EDA tools to automatically optimize layout and routing, predict power consumption and performance. However, compared to top international levels, there is still a gap in algorithms and datasets.
Summary of Domestic Methods: Application-driven, agile development, adept at leveraging mature and open-source ecosystems, achieving rapid breakthroughs in specific fields, but the foundational tools and full-process automation capabilities are still catching up.
2. Foreign Chip Design Architecture Exploration Methods
Foreign giants (such as Intel, AMD, NVIDIA, Apple, Google, ARM) lead the development of methodologies, possessing longer technical accumulation, complete EDA toolchains, and more advanced process technologies, thus exploring more cutting-edge, systematic, and in-depth.
2.1 Highly Automated and Intelligent Design Processes
· Advanced Architecture Simulators and Performance Models:
· GEM5, SST: Modular platforms for computer architecture research that can quickly simulate the performance of different CPU microarchitectures and memory systems.
· GPGPU-Sim: Used to simulate NVIDIA GPU architectures.
· These simulators are several orders of magnitude faster than RTL simulation, allowing for large-scale design space exploration early in the architecture design phase.
· AI/ML-Driven Architecture Exploration:
· Reinforcement Learning: Used for automatic optimization of chip layout, NoC configuration, cache hierarchy, etc. Google has successfully applied RL to TPU layout and routing.
· Bayesian Optimization: Efficiently finds optimal configurations in large design spaces, such as optimizing microarchitecture parameters (pipeline depth, reorder buffer size, etc.) of processor cores.
· Graph Neural Networks: Used for performance and power prediction of complex networks on chips (such as NoC).
2.2 Vertical Integration and Full-Stack Optimization
· Apple Silicon (M series chips): A paradigm. From instruction set, CPU/GPU/NPU microarchitecture, memory subsystems to operating systems (macOS/iPadOS) and application ecosystems (Final Cut Pro, Xcode), achieving deep full-stack optimization for extreme energy efficiency.
2.3 Exploration Based on High-Level Languages and Agile Development
· Chisel (Constructing Hardware in a Scala Embedded Language): An open-source hardware construction language developed by Berkeley. It allows hardware to be described using parameterized generators in high-level programming languages (Scala), enabling rapid derivation of numerous different microarchitecture designs for exploration. The RISC-V benchmark project Rocket Chip was developed using Chisel.
· High-Level Synthesis: Using languages like C/C++/SystemC for behavioral-level descriptions, which are then automatically synthesized into RTL by tools (such as Cadence Stratus, Siemens Catapult), enhancing the design abstraction level.
2.4 Exploration of Future Computing Paradigms
· Approximate Computing: In applications that allow for certain errors (such as image processing), significant power and area savings are achieved by reducing computational precision.
· In-Memory Computing: Exploring embedding computing units within memory to fundamentally address the “memory wall” problem.
· Photonic Computing, Quantum Computing: Conducting foundational research on more distant frontiers.
Summary of Foreign Methods: Technology-driven, full-stack optimization, highly reliant on self-developed advanced EDA methods and AI tools, with exploration directions covering everything from extreme optimization of existing architectures to disruptive future computing paradigms.
3. Common Development Trends and Future Directions
1. AI-Driven Automation: AI will permeate every aspect of architecture exploration, from high-level architectural decisions to low-level physical implementations, achieving “autonomous driving” in chip design.
2. Domain-Specific Architectures: The slowdown in general computing performance improvement makes custom hardware for specific domains (such as AI, bioinformatics, graphics processing) mainstream. DSA is the core direction for the future.
3. Deepening Hardware-Software Co-Design: Architecture exploration is no longer conducted in isolation but is synchronized with compiler, operating system, programming framework, and even application development.
4. System-Level Exploration: Expanding from single chip architecture exploration to Chiplet and heterogeneous integration architecture exploration, requiring consideration of inter-chip interconnect protocols (such as UCIe), packaging technologies, and system-level power/thermal management.
5. Openness and Open Source: RISC-V and open-source hardware design languages (Chisel) are lowering the barriers to architectural innovation, fostering more diverse designs.
In summary, chip architecture exploration is transitioning from an “art” to a highly systematized “science” empowered by data-driven and intelligent algorithms. Both domestic and foreign entities are accelerating in this direction, but foreign giants still hold a significant lead in the forefront of methodology, completeness of toolchains, and depth of exploration.