Automotive SoC chips have become the core “brain” of intelligent driving and smart cockpit systems.
With the continuous advancement of automotive intelligence and connectivity, this article briefly outlines the industrial chain, selection logic, technological trends, and market landscape of automotive SoC chips, focusing on the two major fields of intelligent driving SoCs and smart cockpit SoCs.
Overview of the Industrial Chain
The automotive SoC chip industrial chain covers upstream, midstream, and downstream segments.Upstream includes high-tech barrier fields such as chip IP licensing, EDA software tools, semiconductor manufacturing equipment, and materials. Currently, CPU architecture IP is mainly monopolized by ARM, and EDA tools are controlled by a few giants like Synopsys and Cadence. The design of automotive chips in China heavily relies on these imported IPs and tools. Key semiconductor equipment (such as photolithography machines) is also dominated by overseas manufacturers like ASML, leaving domestic companies constrained by core IP and equipment, raising concerns about supply security and necessitating accelerated localization of key technologies.Midstream involves chip design, wafer foundry manufacturing, and packaging testing. Automotive SoC design manufacturers include international giants (such as NVIDIA, Mobileye, Qualcomm) and local newcomers (such as Horizon Robotics, Black Sesame, and Chipone Technology), many of which adopt a Fabless model focusing on design, with TSMC, Samsung, and other foundries producing advanced process chips (7nm and below high-performance SoCs still mainly rely on TSMC). Domestic wafer manufacturing (such as SMIC) still lags behind foreign counterparts in advanced processes, which may become a bottleneck for high-performance automotive SoCs. In the packaging and testing segment, domestic companies have certain advantages, with local manufacturers like JCET and Huatian Technology providing reliable automotive-grade packaging and testing services.Downstream involves Tier 1 suppliers (such as Bosch, Continental) integrating SoCs into systems like autonomous driving domain controllers and cockpit domain controllers for use by automakers. At the same time, various automakers also participate in chip layout through different models: self-research (such as Tesla’s FSD chip, domestic NIO/Xpeng self-research teams), joint ventures (Geely-Arm China’s ChipQing Technology), strategic cooperation (Leap Motor and Dahua jointly developing the Lingxin 01 chip), or strategic investments (SAIC investing in Horizon Robotics, Black Sesame, etc.) to enhance supply chain control and technological differentiation.
Intelligent Driving SoC Chips
1. Selection Logic and Computing Power Requirements
Intelligent driving (covering L0-L2 level ADAS to higher-level autonomous driving) has extremely high requirements for the computing power, power consumption, and reliability of SoC chips, with significant differences in chip specifications required for different scenarios. When selecting chips, automakers need to comprehensively consider factors such as functional level, computing power requirements, cost, power consumption, and ecological support, seeking a solution that is “sufficient and efficient“.
L0-L1 level forward ADAS: Typically adopts a front-view camera integrated solution, which integrates the camera module, processor, and algorithms together, consisting ofa medium computing power SoC + a safety MCU. The SoC is responsible for image processing and target recognition calculations, while the safety MCU acts as an independent “safety core” executing functional safety tasks related to vehicle control (requiring ASIL-D level). Typical chips include Mobileye EyeQ4, Horizon Journey 2/3, or Texas Instruments TDA4VM, which can support basic driver assistance functions such as forward collision warning (AEB), adaptive cruise control (ACC), and lane keeping assistance (LKA). This type of solution is cost-effective (a 2M pixel camera solution costs about 500-600 RMB), has low power consumption, and is suitable for quickly adding ADAS features to entry-level models priced at 100,000-150,000 RMB. Low power consumption is particularly important for integrated solutions, as the devices are usually installed in the limited space near the front windshield, where heat dissipation is constrained, and only low-power chips can avoid overheating and reduce the stringent requirements for heat dissipation and power supply.
L2 level integrated driving and parking domain control: When the functional upgrade covers L1-L2 level driving assistance and automatic parking (APA)/360-degree surround view parking functions, the system expands from a single sensor tomulti-sensor fusion. The industry has begun to adopt a single SoC domain controller solution that runs driving + parking continuously, meaninga single SoC processes all driving and parking sensor data in parallel, rather than switching modes as in earlier solutions. Continuous fusion can avoid perception blind spots or poor experiences caused by insufficient computing power during mode switching. For example, in the automatic parking (AVP) scenario, the vehicle needs to find a parking space using the surround camera and ultrasonic radar in coordination, and may also use the front-view camera or millimeter-wave radar to detect distant obstacles; in the driving scenario, parking sensor data may also be needed for assistance, and only full-time collaboration of sensor data can provide seamless perception. This places high demands on the parallel processing capability of the SoC. Experience suggests that to support a single SoC for a driving and parking integration solution with 5 cameras + 5 radars (5V5R) or 6 cameras + 5 radars (6V5R), the CPU computing power must be at least 20 KDMIPS, and AI computing power must exceed ten TOPS. Common combinations currently include:Single SoC (such as a single TI TDA4VM/VH, Black Sesame Huashan A1000 series, NVIDIA Orin-NX/Orin-N, or Ambarella CV series, etc.),Multiple SoCs (such as dual TDA4VM, dual Horizon Journey 3, or even combinations of “three Journey 3” or “Journey 2/3 + TDA4VM”). However, multi-SoC architectures require each chip to be paired with independent storage and power management, and high-speed communication between chips, increasing system complexity, power consumption, and cost. As single-chip computing power improves, multi-SoC solutions are gradually giving way to single-SoC architectures. In recent years, chips like Horizon Journey 5 and Ambarella CV3 with hundreds of TOPS have been launched, making it possible for mid-range models to achieve integrated driving and parking with a single chip. In actual projects, automakers do not blindly pursue maximum computing power but focus more on balancing computing power and cost—blindly stacking computing power can lead to high costs and loss of competitiveness, thus “sufficient is good” has become the pragmatic selection criterion for mainstream models.
In addition, during the chip selection process, OEMs and Tier 1 suppliers also value thehidden value that the solution can bring to R&D and mass production, including:
a. Platform Continuity: Whether the chip supplier has a clear product iteration roadmap and continuous upgrade capability, can provide a family of chips with high and low configurations of the same series, facilitating smooth upgrades for automakers in subsequent models, reducing the high costs and risks of switching platforms. For example, Horizon emphasizes that the architecture of the Journey series is consistent across generations and compatible between generations, providing a family of chips from low to high computing power for customer expansion.
b. Adaptability: Whether the SoC can fully integrate with other hardware and software in the vehicle, including hardware interfaces (camera, radar interface quantity and type, storage and communication bus support, etc.), software environment (operating system, middleware, algorithm compatibility), and vehicle network protocols (CAN, Ethernet, etc.). Good adaptability ensures that the chip can easily integrate into the vehicle’s electronic and electrical architecture without causing functional bottlenecks due to interface mismatches or hardware-software coordination issues.
c. Platform Design: Whether the chip provides a series platform solution, facilitating Tier 1/automakers to support different model needs with one platform, reducing development and maintenance costs. Practice shows that deeply cultivating a unified platform is often more efficient than changing different chips for each project. Some suppliers have adopted a strategy of usingthe same series of chips flexibly to meet multiple projects, enhancing profits and building reputation. For example, Horizon’s Journey 6 series provides multiple chips with a unified architecture and toolchain, facilitating customer development and reuse.
d. Software Ecosystem: A complete software stack significantly reduces the difficulty of secondary development for automakers. This includes a rich and stable operator library, easy-to-use AI development toolchain, and reliable driver, operating system, and middleware support. A strong ecosystem allows automakers to shorten development cycles and reduce costs. For example, NVIDIA has gathered a large number of developers through the CUDA development tools and Drive software platform, becoming an industry-recognized software ecosystem benchmark. In contrast, the ecosystem of emerging domestic chip companies remains a shortcoming that requires continuous investment to improve.
e. Local Support: The automotive R&D cycle is tight, and from prototype validation to mass production, many hardware and software issues arise, making rapid local support from chip manufacturers crucial. If suppliers have sufficient engineering teams in China to collaborate with automakers for debugging (covering hardware design consulting, algorithm porting and optimization, driver adaptation, etc.), it can accelerate project implementation; conversely, inadequate support can pose significant risks to automakers. Therefore, a major advantage of domestic manufacturers over overseas ones is the proximity of local teams to customers and efficient response, with many startup chip companies even stationed on-site at automakers to ensure smooth mass production of products.
In summary, intelligent driving SoCs that stand out are often those with both hardware and software capabilities: they can meet requirements in terms of computing power, power consumption, functional safety, and also provide a complete software ecosystem and timely local service, minimizing the uncertainty of vehicle development.
2. Chip Architecture Evolution and Technological Trends
As autonomous driving algorithms evolve from rule-based/CNN to new architectures like BEV perception, Transformer networks, and Occupancy Grid, SoC chip design is also facing new challenges. The computing characteristics of the Transformer model are entirely different from CNN—CNN is mainly based on rule convolution, is computation-intensive, and has strong locality in data access; while Transformer is filled with matrix transpositions and tensor operations, making it memory-intensive and requiring extremely high on-chip storage capacity and bandwidth. Many traditional automotive AI chips optimized for CNN are often inefficient when facing Transformer, and simply quantizing Transformer networks to INT8 precision does not solve the problem, but rather leads to a significant drop in performance due to quantization errors. To adapt to these emerging algorithm models, the next generation of automotive SoCs is showing the following evolutionary directions in architecture:
a. Introduction of Transformer-specific acceleration units: To bridge the gap between traditional AI chips and Transformer models, leading manufacturers have begun to integrate dedicated Transformer Engine acceleration modules into their chips. For example, NVIDIA has added a Transformer Engine unit in its latest Hopper GPU architecture, applied to the automotive-oriented Drive Thor chip, supporting FP8/FP16 mixed precision computing and dynamic computation graph scheduling, significantly accelerating Transformer model training and inference. In the future, high-performance SoCs for automotive AI are likely to include dedicated hardware for Transformer, GNN, and other new networks. Domestic manufacturers are also proactively laying out related IP (such as variable-length attention acceleration), allowing automotive AI chips to no longer be limited to CNN models.
b. Optimizing operators and enhancing toolchain flexibility: Considering the emergence of new algorithms, chips cannot exhaustively adapt to all models in advance. A pragmatic path is to optimize core operators and provide evolving toolchain support. For example, the core attention mechanism of Transformer involves matrix multiplication, Softmax, and other computations; as long as the chip architecture supports these operations in principle and reserves sufficient programmable flexibility, it can adapt to new models through compiler and library upgrades later. Most AI networks’ main overhead is concentrated on a few hotspot operators, which can be significantly improved in efficiency through hardware acceleration. For instance, Horizon’s new generation Journey 6 chip has added hardware acceleration units for operators like LayerNorm and Softmax, as well as acceleration for tensor transposition/reshape, reportedly optimizing some operators that only account for 3% of the model’s computation but consumed 10-30% of the runtime, significantly improving the overall efficiency of Transformer networks. At the same time, it is essential to ensure that the compiler/driver has sufficient flexibility, allowing engineers to continuously explore the chip’s potential and support new operators without modifying the hardware.
c. Breaking through the “Memory Wall” bottleneck: Under the von Neumann architecture, the separation of computing units and storage units leads to frequent data transfers, causing theMemory Wall problem. Models like Transformer have massive parameters and complex structures, posing unprecedented challenges to on-chip SRAM capacity and bus bandwidth: in recent years, the parameter count of large models has surged hundreds of times, with computation increasing hundreds of times. Even if automotive applications do not deploy models with billions of parameters, the parameter scale of Transformer on vehicles has far exceeded that of traditional CNN, leading to a surge in computing power demand. If the past cache/memory system is used, chips will struggle to “feed” these greedy models. Therefore, the new generation of SoCs focuses on optimizing on-chip memory structure and bandwidth. For example, Horizon’s Journey 6 adopts a multi-level storage architecture (L0/L1/L2) combined with advanced on-chip buses and high-bandwidth DDR to alleviate memory access bottlenecks as much as possible; Ambarella CV3 innovatively divides on-chip SRAM into different sizes of Partial Buffers (local cache areas) specifically for storing intermediate computation results, significantly reducing the number of accesses to off-chip DRAM. These improvements enhance data localization processing capabilities, reduce ineffective data transfers, and improve actual computing power utilization. In the future, more storage levels, faster on-chip interconnects (such as on-chip optical interconnects), and even storage-computing integration technologies may gradually be applied to automotive SoCs to break through the “Memory Wall.” It can be anticipated that the competition for computing power is also a competition forbandwidth: whoever can better solve the data supply bottleneck will be able to truly unleash peak performance of their chips.
This round of algorithm paradigm shift presents both challenges and opportunities for chips. As everyone is almost starting from the same starting line, domestic manufacturers have the opportunity to achieve “curve overtaking” through architectural innovation. Currently, some local companies are showing keen insight, attempting differentiated technological routes (such as introducing RISC-V architecture, NPU support for reconfigurable computing, etc.). Of course, architectural evolution requires bold ideas, but also consideration of implementation complexity and mass production feasibility. Automotive chips must ultimately withstand the test of engineering implementation; it is not about having higher computing power, but about targeted optimization of key paths under limited power consumption and cost. In the coming years, the architecture of automotive SoCs mayblossom: some will focus on visual computing acceleration, some will enhance general CPU processing of rule logic, and some will use Chiplet technology to heterogeneously integrate various IPs. Regardless of the route, the goal is to provide sufficient computing power to meet the growing intelligence demands of vehicles. Those who can keep up with or even lead the pace of algorithm evolution will gain an advantage in the competition for the next generation of automotive chips.
Smart Cockpit SoC Chips
Compared to intelligent driving, which focuses on environmental perception and decision-making, smart cockpit SoCs mainly serve in-vehicle human-machine interaction and entertainment experiences, emphasizing multimedia processing, display output, and AI interaction capabilities. As the cockpit electronic architecture transitions from decentralized to centralized, the keywords for cockpit development have become “one chip multiple screens” “multi-modal interaction” “cockpit-driving integration“. The selection of cockpit SoCs needs to balance graphical performance, AI computing power, ecological compatibility, and cost power consumption, mainly considering the following aspects:
One chip multiple screen capability: The new generation of cockpit domain controllers requiresa single high-performance SoC to drive multiple screens (digital instrument, central control large screen, head-up display (HUD), co-driver entertainment screen, rear entertainment screen, etc.), outputting high-resolution images while ensuring smooth interface animations and video playback without stuttering. This requires the chip to have powerful GPU rendering and multi-channel display output capabilities, with a rich array of display interfaces. Some leading cockpit chips are equipped with multiple display controllers and GPU virtualization features, allowing multiple operating system environments (such as running Android cockpit systems and real-time operating systems for driving instruments simultaneously) on a single SoC, ensuring that different screens can collaborate and isolate, meeting both functional safety and user experience requirements. When selecting chips, automakers will pay attention to the maximum number of screens supported, resolution/frame rate, and the ability to support multiple systems in parallel. In the trend of multi-screen cockpits, “one chip cannot support multiple screens” solutions will be unable to meet future demands. Current mainstream cockpit chips (such as Qualcomm Snapdragon 8155 platform) generally claim to support one chip multiple screen output, and domestic manufacturers are also racing to catch up with corresponding capabilities.
Multi-modal intelligent interaction integration: Cockpit interaction is expanding from traditional button touch tovoice, gesture, vision, and other multi-modal fusion. Therefore, the SoC needs to have certain AI computing power and signal processing capabilities to handle tasks such as voice recognition and image processing, and provide the necessary sensor interface support. For example, the cockpit often arrangesmicrophone arrays for voice interaction, and the chip needs high-performance DSP or NPU to perform echo cancellation, noise reduction, voice activation detection, and other preprocessing, as well as voice recognition and natural language understanding. Similarly,in-vehicle cameras are used for driver monitoring (DMS), passenger monitoring (OMS), and gesture recognition, which were previously handled by independent ECUs, but as the performance of cockpit SoCs improves, these functions are gradually integrated into the main SoC. Modern cockpit SoCs typically include ISP image processors and neural network accelerators, allowing direct access to in-vehicle cameras to implement functions such as detecting driver distraction/fatigue, passenger behavior recognition, and gesture control. Functional integration not only reduces the additional ECU hardware costs but also allows various interaction functions to collaborate more closely with the cockpit entertainment system (for example, when detecting that the driver is dozing off, the cockpit system automatically lowers the music volume and issues a warning). When selecting, automakers will evaluate the SoC’s support for these AI interaction tasks: includingNPU computing power sufficient to run the required models,the number/type of camera interfaces (RGB or infrared) meeting the requirements, and whether the DSP supports advanced voice algorithm libraries, etc. If a chip is significantly lacking in voice or visual AI capabilities, it will not be able to meet the increasingly intelligent cockpit demands.
Integration of cockpit and driving and central computing trends: A noteworthy frontier trend is theintegration of smart cockpit and intelligent driving domains. As the overall vehicle electronic and electrical architecture evolves towards centralization, some automakers envision replacing the current cockpit and driving domain controllers with a central supercomputing platform that uniformly processes in-vehicle and external perception and decision-making, achieving “cockpit-driving integration” for overall collaborative services. For example, a central AI can comprehensively analyze external road conditions and the status of in-vehicle occupants to decide whether to activate specific driving assistance functions or human-machine interface prompts. Given safety isolation and other factors, most models still deploy cockpit and ADAS domains separately, but preliminary signs of integration have emerged: some models integrate ADAS warning functions into the cockpit system, issuing front collision alerts through the central control screen or voice output; conversely, ADAS systems also utilize cockpit DMS camera data to enhance understanding of driver intent. This bidirectional data and function connectivity places higher demands on chips, requiring them to possess both automotive-grade functional safety and high computing power heterogeneous computing capabilities. Therefore, some believe that the ultimate chips capable of handling both cockpit and autonomous driving tasks will be those with automotive-grade safety architecture and powerful GPU/NPU acceleration units, referred to as “automotive supercomputing” chips. Currently, high-end SoCs like NVIDIA Orin are already performing both cockpit and ADAS duties in some mass-produced models, and domestic manufacturers are also developing chips that support multi-domain integration. Although the complete era of cockpit-driving integration has not yet truly arrived, forward-looking automakers are beginning to consider the chip’s extensibility and redundant computing power when selecting, so that hardware does not need to be replaced during future architectural adjustments. In the trend of central computing, highly integrated and flexible chip platforms are undoubtedly more viable.
It is worth noting that the success or failure of smart cockpit chips largely depends onsoftware ecosystem and automotive-grade reliability and other soft indicators. The cockpit system ecosystem (mainly referring to the Android vehicle system and its applications) has become quite mature and stable after years of development,compatibility with existing ecosystems is crucial—this is why Qualcomm chips occupy a large portion of the market, as their support for the Android system is comprehensive, and third-party application compatibility is widespread. If domestic cockpit chips cannot run mainstream operating systems and applications smoothly, even with excellent hardware specifications, they will struggle to gain favor from OEMs. In addition, cockpit SoCs need to meet automotive-grade stability and safety requirements, such as24/7 reliable operation, rapid cold start under extreme temperatures, and hardware and software security protection for user privacy data, etc. These requirements can usually only be proven through real vehicle mass production verification, which is a threshold that newcomers must cross. Overall, the selection of smart cockpit chips is shifting from purely comparing performance parameters tocomprehensive experience orientation: solutions that can provide better human-machine interaction experiences, support more innovative applications, and are reliable and safe are the ideal choices for automakers.
Industry Landscape and Domestic Substitution
1. Intelligent Driving SoC Market Landscape
As of 2023, the global intelligent driving SoC market landscape has initially formed, showing a trend of foreign dominance and domestic rise. Currently, overseas solutions account for over 80% of the market share of autonomous driving computing chips installed in vehicles, with Tesla’s self-developed FSD chip and NVIDIA Orin-X being the most prominent, together accounting for about 70%. Tesla’s FSD is a unique case of self-research by an automaker, used only in its own models (each vehicle is equipped with two FSD chips); while NVIDIA Orin-X, with its mature software and hardware ecosystem, has become the de facto industry standard platform, adopted by many domestic new forces such as NIO, Li Auto, Xpeng, Zhiji, and Jidu. In addition, Mobileye’s EyeQ4/5 generation chips still have considerable installation volume in the forward ADAS market, with the 2023 shipment of EyeQ4H being approximately equivalent to Horizon Journey 5 (both around 200,000 units). Many Tier 1 suppliers (such as Continental, Bosch) also use chips or FPGAs from European and American companies like NVIDIA and Xilinx in their autonomous driving domain controllers.
Despite currently being at a disadvantage, domestic intelligent driving chips are achieving breakthroughs from 0 to 1. Horizon’s Journey 5 chip is expected to ship about 200,000 units in 2023, capturing about 6% market share, becoming the first domestically produced high-performance autonomous driving SoC to achieve large-scale pre-installation. The launch of models equipped with Journey 5, such as Li Auto L7/L8 and BYD Han, marks that domestic solutions have the capability to operate stably in real road scenarios. It is important to emphasize that the intelligent driving SoC market is far from solidified, and all players still have competitive opportunities. Domestic manufacturers are more flexible and responsive in local service and demand, coupled with geopolitical factors prompting automakers to “reduce foreign dependence,” leading to a noticeable increase in OEMs’ enthusiasm for introducing domestic chips recently. For example, BYD, SAIC, and others have been collaborating or investing with domestic chip companies, creating favorable conditions for domestic solutions to increase market share. However, to truly catch up with foreign leaders, domestic manufacturers must face challenges: first, they need to continuously catch up technologically, especially to ensure that the computing power and energy efficiency of high-end chips reach world-class levels; second, they must build ecosystems and scale effects to attract more algorithm developers to prioritize adapting to domestic platforms, forming a virtuous cycle. Overall, the intelligent driving chip field is expected to enter a phase of competition among various players in the coming years—foreign giants accelerating innovation to consolidate their advantages, while domestic newcomers strive to catch up and find differentiated entry points. This competitive landscape will bring faster technological progress and better cost options, which is a welcome situation for automakers and consumers alike.
2. Intelligent Cockpit SoC Market Landscape
Intelligent cockpit SoCs have seen rapid increases in installation rates in passenger vehicles due to relatively low entry barriers and high demand. Statistics show that the installation rate of cockpit SoCs in Chinese passenger vehicles has exceeded 50%, with mid-to-high-end models basically achieving standard digital cockpit configurations. However, beneath the prosperous surface, the market share of domestic cockpit chips is less than 10%. This means that most of the market is occupied by foreign manufacturers such as Qualcomm, Intel (early Atom/Aptiv series), Texas Instruments, and NXP. Domestic companies, having started later, have only achieved breakthroughs in a few models, such as Chipone Technology’sX9 chip being applied in Hongqi H9, and Horizon previously collaborated with MediaTek to launch a cockpit AI assistance chip Journey 3 (providing AI acceleration in conjunction with MediaTek’s main chip), as well as solutions from Rockchip and Allwinner, former consumer electronics chip manufacturers, being trialed in some low-end models. However, overall, the large-scale pre-installation of domestic cockpit chips is still in its early stages.
The reasons for the low market share of domestic cockpit chips are mainly twofold: first, domestic manufacturers entered the market late and need to face strong competitors like Qualcomm, which have been deeply entrenched for many years; second, cockpit systems are highly dependent onsoftware ecosystems. Manufacturers like Qualcomm have accumulated a wealth of compatibility optimization experience and customer resources in the Android vehicle ecosystem, while new entrants need time to establish and refine their ecosystems. In addition, many automakers’ infotainment system development is completed by external suppliers (such as Bosch providing a complete cockpit solution), and these suppliers tend to prefer mature chip platforms to reduce risks, inadvertently raising the threshold for domestic chips to enter mainstream models.
However, domestic cockpit chips are not without opportunities. The booming market for new energy vehicles in China, with rapid model updates and brands emphasizing intelligent differentiation, provides fertile ground for local chips tocatch up. Domestic manufacturers have already seized the “timing” and “geographical advantages”: the domestic market is growing rapidly, and there is a strong willingness for local substitution. As long as product maturity meets standards, automakers are willing to try introducing domestic chips to create the selling point of “Chinese manufacturing intelligence.” In recent years, there have been some cases: the Leap S01 model was the first to adopt domestic processors, achieving a breakthrough; SAIC, BYD, and others are also jointly developing or procuring domestic cockpit chips for some new models. It is foreseeable that the installation proportion of domestic cockpit chips in mid-to-low-end new energy models will gradually increase, and it is expected to break through 10% or even higher in a few years. Especially in the current context of overcapacity in consumer electronics chips, some mobile SoC manufacturers (such as Unisoc, HiSilicon) may become market disruptors by adjusting their strategies to enter the automotive field, accelerating the evolution of the cockpit chip landscape. Of course, domestic manufacturers must also gain long-term recognition from Tier 1 suppliers and automakers in terms of stability and adaptability, and boost industry confidence through the large-scale adoption of one or two phenomenal models to gradually eliminate doubts.
3. Current Status and Prospects of Domestic Substitution
“Domestic substitution” has become a high-frequency buzzword in the automotive semiconductor field in recent years. From national policies to OEM strategies, there is an emphasis on increasing the self-sufficiency rate of domestic chips to ensure supply chain security and control key technologies. In the subfield of automotive SoCs, the progress of domestic substitution can be described asmixed blessings: in the intelligent driving domain, companies like Horizon have achieved breakthroughs from 0 to 1, with domestic solutions beginning to enter mass-produced vehicles, but high-performance chips still mainly rely on foreign sources; in the cockpit domain, domestic penetration is even lower, but the prospects are viewed positively by the industry.
It should be noted that “substitution” does not mean blindly rejecting foreign products, but rather refers to introducing more domestic solutions to optimize supply chain structures after comprehensively considering supply security, cost, and performance. In practice, automakers often adopta multi-supplier strategy: high-end models continue to use the most mature overseas chips, while mid-to-low-end models attempt to use domestic chips, dispersing risks across different projects. This ensures that high-end products maintain performance and competitiveness while supporting the cultivation of the local supply chain. For example, a certain domestic brand’s flagship model still uses Qualcomm 8155 chips, but its entry-level electric vehicle model has opted for Chipone Technology’s cockpit SoC paired with a domestic operating system. Once domestic solutions perform close to expectations, the adoption range for subsequent mid-to-high-end products may gradually expand.
In the vigorous promotion of domestic substitution, it is also necessary to maintain rationality and patience. On one hand, automotive chips relate to driving safety and user experience, and any performance shortcoming or reliability issue could lead to serious consequences. If immature domestic chips are rushed into production, problems will undermine industry confidence. Therefore, substitution should follow the principle ofgradual progress, first validating in secondary functions or low-risk scenarios before expanding applications once mature. On the other hand, domestic manufacturers should also be wary of overly relying on policy support and relaxing their R&D investments. Ultimately, the market speaks through product strength; only when domestic chips truly achieve “user-friendly and affordable” in terms of performance, cost, and ecosystem will automakers adopt them in large quantities, and domestic substitution will naturally follow. Historical experience shows that companies that grow in a fully competitive environment are the most resilient. Fortunately, we have already seen many local chip companies develop from 0 to 1, winning customer trust by solving practical problems rather than relying solely on policy support.
Looking ahead, as China’s automotive industry begins to lead globally in the fields of new energy and intelligence, the automotive SoC chip market will also enter a new round of reshuffling. Domestic and foreign manufacturers will compete on the same stage, jointly promoting technological progress. Perhaps in a few years, when looking back, “domestic substitution” will no longer be a challenge for the industry—by then, the market will feature chips from both NVIDIA and Mobileye, as well as those from Horizon and Black Sesame, each showcasing their strengths and meeting their needs. This is the healthy industrial ecosystem that should exist. With the collaborative efforts of all segments of the industry chain, the field of automotive SoCs in China will ultimately transition from “catching up” to “running alongside” or even “leading,” contributing more “Chinese chip” power to global automotive intelligence.
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