Design of an FPGA-Based Image Compression Codec System

2020 Electronic Technology Applications, Issue 12

Abstract: In response to the real-time requirements of image processing, an FPGA-based image compression codec system has been designed. This system includes functions such as real-time image acquisition, JPEG compression, and UART transmission. The Altera DE series development board is used, and the D5M camera is configured using Verilog HDL hardware description language to complete image acquisition. In the image compression module, improvements are made to the 2D-DCT transformation. Based on the Chen algorithm, a binary frequency signal controller is employed to reduce the calls to adders, achieving fast computation and thus completing the image compression function. In the UART transmission module, the main task is to convert between serial and parallel communication. Tests show that the compression ratio of the image reaches 26.3:1, with an average signal-to-noise ratio greater than 40 dB, and the visual effect after compression is good, meeting design requirements.

Keywords: FPGA, JPEG compression algorithm, RS_232, D5M camera

0 Introduction

The amount of information carried by digitally processed images is enormous, which severely affects image storage and transmission. Therefore, image compression has significant practical importance [1-2]. In actual engineering demands, due to the large volume of image data and the requirement for real-time processing, relying solely on software for image processing is often very time-consuming. Thus, using hardware that can perform parallel processing can greatly accelerate data processing speed and provide higher flexibility in program design.

This design uses the FPGA development platform as the control core of the entire system, acquiring real-time images via the I2C bus and converting them into RGB format image data in real-time. The JPEG algorithm is utilized to encode the Y, Cb, and Cr components separately, programmed in Verilog HDL, significantly speeding up processing. The compressed data stream is transmitted to a PC via the RS_232 serial port, and finally imported into MATLAB for decompression and image restoration.

Design of an FPGA-Based Image Compression Codec System

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