Design of a Real-Time Airborne Channel Simulator Based on CPU and FPGA

Title:Design of a Real-Time Airborne Channel Simulator Based on CPU and FPGA

Authors:Lu Hui, Liu Xueyan

Abstract

Channel modeling is a fundamental and important method for studying near-space communication technology and evaluating system transmission characteristics. As near-space vehicles evolve from low-speed to high-speed, the frequency of channel changes increases with the speed of the vehicle. To achieve real-time simulation of channel fading during airborne communication, a channel simulator based on a Central Processing Unit (CPU) and a Field-Programmable Gate Array (FPGA) architecture is developed, with parameters updated every 1 ms. This simulator incorporates a meteorological loss model and a wireless channel fading model. The CPU side compresses the computation time of channel parameters by designing a state machine control module, optimizing parameter calculation logic, and optimizing the operating system. The FPGA part designs a key information synchronization scheme and a state machine-based dual assurance update mechanism to ensure reliable and stable transmission of parameters, while parallel acceleration processing enhances information interaction and signal processing speed. Experimental results show that the proposed scheme effectively improves the parameter calculation speed and signal processing speed of the airborne channel simulator, achieving a 1 ms update of channel parameters with the movement of the transceiver.

Lu Hui, Liu Xueyan. Design of a Real-Time Airborne Channel Simulator Based on CPU and FPGA. Computer Measurement and Control[J]., 2023, 31(11):286-292.

Design of a Real-Time Airborne Channel Simulator Based on CPU and FPGA

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Design of a Real-Time Airborne Channel Simulator Based on CPU and FPGA

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