1 Introduction
In the process of information signal processing, filters are used for tasks such as signal filtering, detection, and prediction. Digital filters are the most widely used devices in digital signal processing (DSP). The commonly used filters are Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. Among them, FIR filters can provide ideal linear phase response, achieving constant group delay across the entire frequency band, resulting in zero distortion output signals. Additionally, they can be implemented using very simple algorithms. These two advantages make FIR filters the preferred choice for wise design engineers. When designing digital filters using hardware description languages such as VHDL or Verilog HDL, the performance of the filter often does not meet good optimization due to the programming involved. However, using well-debugged IPCore requires purchasing from Altera. The author adopts an FPGA design method based on DSPBuilder, which simplifies the FIR filter design and meets design requirements.
2 Introduction to FIR Filters
2.1 Principle of FIR Filter Design
r is the number of taps of the FIR filter; b(r) is the r-th tap (unit impulse response); x(n-r) is the input signal delayed by r taps.
The task of designing a filter is to seek a causal, physically realizable system function H(z) such that its frequency response H(e^{jw}) meets the desired frequency domain specifications.
2.2 Design Requirements
A digital filter is essentially a linear, time-invariant discrete system implemented using finite precision algorithms. Its design steps involve first determining the performance specifications, designing a system function H(z) to approximate the required technical specifications, and finally implementing it using finite precision algorithms. The design specifications for this system are: to design a 16th-order low-pass filter with a sampling frequency of fs = 48KHz and a cutoff frequency fc = 10.8kHz, with an input sequence bit width of 9 bits (the most significant bit being the sign bit).
3 Introduction to DSPBuilder
DSPBuilder is a DSP development tool launched by Altera, which integrates Mathworks’ Matlab and Simulink DSP development software in the Quartus II FPGA design environment.
Previously, the use of Matlab tools often served as modeling for DSP algorithms and pure mathematical simulation. The mathematical models could not directly generate practical program code for hardware DSP application systems, and the results of simulation tests were based solely on mathematical algorithm structures. Traditional FPGA designs based on hardware description languages (HDL) were complicated due to the need to consider the δ delay of FPGA hardware and the integration of recursive algorithms in VHDL, as well as issues such as two’s complement operations and product result truncation.
For DSPBuilder, the top-level development tool is Matlab/Simulink, and the entire development flow can be completed in the same environment, truly realizing a self-directed design process. This includes modeling of the DSP system, system-level simulation, conversion of design models to VHDL hardware description language code, RTL (Register Transfer Level) functional simulation testing, compilation adaptation, layout and routing, timing real-time simulation, and programming configuration of DSP target devices. The entire design process seamlessly integrates system description and hardware implementation, showcasing the characteristics and advantages of modern electronic design automation development.
4 DSPBuilder Design of FIR Digital Filter
4.1 Parameter Selection for FIR Filter
Using the dedicated toolbox for filter design provided by Matlab—FDATool—to simulate and design the filter, meeting the required FIR filter amplitude-frequency characteristics. Since floating-point implementation in FPGA is quite difficult and costly, the filter coefficients and input data need to be converted to integers. The quantized coefficients can be directly converted in the Matlab main window, while the input data can be multiplied by a certain gain and controlled by Altbus to convert to integer input.
According to the principle of FIR filters, FPGA can be used to implement the FIR filtering circuit. The first step in the DSPBuilder design process is to perform design input in Matlab/Simulink, which involves creating an MDL model file in the Simulink environment, graphically calling Altera DSPBuilder and other graphical modules from the Simulink library to form a system-level or algorithm-level design block diagram (also known as Simulink modeling).
4.3 FIR Filter Simulation Based on DSPBuilder
The input signals consist of two sine waves with frequencies f1 = 8KHz and f2 = 16KHz superimposed. The simulation waveform is shown in Figure 3. From the simulation results of the FIR filter circuit, it can be seen that after passing through the filter, the output signal has essentially become a single-frequency sine wave. Further analysis with a spectrum analyzer shows that f2 has been significantly suppressed, which is in line with the conditions specified for the low-pass filter with fc = 10.8kHz. Thus, the model simulation is complete.
4.4 Functional Simulation Using Modelsim
The simulation conducted in Simulink is of a system verification nature, simulating the MDL file without simulating the generated VHDL code. In fact, the generated VHDL description is at the RTL level, targeted at specific hardware structures, while the model simulation in Matlab’s Simulink is at the algorithm level (system level), focused on algorithm implementation. There may be differences in software understanding between the two, and the converted VHDL code implementation may not fully correspond to the MDL model description. This necessitates functional simulation of the generated RTL-level VHDL code.
Here, the author uses Modelsim to perform functional simulation of the generated VHDL code. Input and output signals are set to analog form, resulting in the simulation waveform shown in Figure 4, which is consistent with the simulation results in Simulink. The hardware design can now proceed in the Quartus II environment.
4.5 Implementing FIR Filter in FPGA Device
Open the Quartus II project file firl.qpf established by DSPBuilder in the Quartus II environment. Perform simulation again in Quartus II, where the required timing waveforms can be observed. Then, specify the device pins and compile, finally downloading to the FPGA device for hardware testing. By adding a CLOCK signal and an enable signal, and using a signal generator to produce the two required sine signals of different frequencies, the filtered results can be observed on the oscilloscope. When designing different filter circuits, only the FIR filter model file needs to be modified, which not only avoids the cumbersome VHDL programming but also facilitates adjustments.
5 Conclusion
When developing digital filters using FPGA, adopting DSPBuilder as a design tool can accelerate the progress. Of course, in practical applications, due to influences from precision, speed, and device selection, the converted VHDL may require further optimization.
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