The concept of DMA is not complicated; it reduces the CPU load by actively managing data transfer. However, there are significant differences in DMA functionality and performance across various STM32 MCU models, which I still find somewhat unclear. Here, I will summarize some points to clarify my thoughts.
There are summaries online regarding the main differences between the F4 and F1 series DMA controllers:
1. The concept of DMA streams has been introduced.
2. Each data stream has a configurable FIFO buffer. (Do not assume that FIFO sizes are configurable; F1 does not allow this.)
Burst transfer: This refers to a single DMA request triggering multiple data transfers. When the source and destination data widths differ or the number of bursts varies, a FIFO is needed for buffering.
I used to be unclear about the concept of streams; I understand it as a data-oriented function, but how does it differ from channels?
Streams do not exist in the F1 series; a peripheral can only perform DMA transfers through a specified channel. In the F4 series, both stream and channel can enable a peripheral’s transfer request, but note that multiple channels corresponding to a single stream cannot be enabled simultaneously. This must be configured using selection before use.
From the STM32Fxx series to the Hxx series, there have been significant changes.
These include, but are not limited to, the following aspects, which I will note as I am not very familiar with them:
1. The H5xx series has an MDMA (Advanced DMA) with higher performance, featuring an independent clock domain and bus.
2. Linked lists: Not supported in the F series, but supported in the H5 series. The linked list records the parameters needed to trigger transfers, and the DMA will automatically execute the recorded tasks according to the linked list, eliminating the need for manual configuration.
3. Trigger sources: The F series has fixed peripheral request mappings, while the H5 series offers more flexible triggers, including signals from the event system.
4. In the STM32F4 DMA, peripheral request signals are fixedly wired to specific DMA channels, but the H5 series has implemented a completely free configuration request mapping mechanism. The H5 introduces a DMA request router, where DMA requests first reach a “routing network” to achieve arbitrary channel configuration. (In the H7, this has evolved into DMAMUX.)
5. FIFO size:
H5:
• GPDMA: Each channel has an independent 16-byte (4 words x 32 bits) FIFO.
• MDMA: Each channel has an independent 32-byte (8 words x 32 bits) FIFO.
F4:
• Each data stream has a 4-word (16-byte) FIFO.
Double buffering mode: I have seen some introductions online; some are hardware-supported, but the specific models are not clear. Most implementations actively manage double-buffered data storage at the software level, serving as a cache.
Talking to myself:
It is still better to test the DMA actions to have a deeper impression.