Behind the 7nm circuits of mobile phone chips and the 10nm flying height of computer hard disk heads lies a key technology – Chemical Mechanical Polishing (CMP). It is currently the only process capable of achieving “global planarization” of silicon wafers. Without it, the reduction in device size and multilayer interconnections would become a “castle in the air.” Today, we will dissect the core logic of CMP technology, its global application status, and the “headaches” it has yet to resolve.
1. Why is CMP an “Essential Need” for Semiconductors? Without it, chips cannot be made more refined.
As Moore’s Law progresses, semiconductor devices face a core pain point:The surface must be sufficiently flat.
- As device sizes shrink from 0.35μm to 7nm, the depth of focus of lithography equipment becomes increasingly shallow (at the nanometer level). Even minor undulations on the silicon wafer surface can lead to circuit misalignment and short circuits;
- Traditional planarization technologies (such as thermal reflow and sputtered glass SOG) can only achieve “local flattening,” such as filling small pits or smoothing small steps, and cannot make the entire silicon wafer surface uniformly flat, which is termed “local planarization”;
- In contrast, CMP is the only process that can achieve “global planarization” – regardless of the size of the silicon wafer (from 200mm to 300mm), it can control the surface undulations at the nanometer level, perfectly meeting the needs of sub-micron (below 0.35μm) devices.
The rapid development of CMP also confirms its importance:
- In 1991, IBM first applied CMP in the production of 64Mb DRAM, leading to its rapid proliferation;
- By the time of the document’s publication (2002), the demand for CMP equipment had tripled in three years, with an expected annual growth of 60%;
- The United States is the largest market (focusing on multilayer devices), while Europe, Japan, South Korea, and Taiwan have all introduced it. For example, seven top IC manufacturers in Japan used CMP for 0.35μm devices, while at that time, no domestic company could produce CMP equipment, highlighting the growing contradiction in multilayer wiring flattening.
2. The “Core Team” of CMP: 4 Major Components + 2 Key Assistants, All Are Essential
CMP is not a single device but a combination process of “chemical etching + mechanical grinding.” Its core relies on the collaboration of four major components, along with post-cleaning and endpoint detection, to achieve precise planarization.
1. Polishing Machine: The “Workstation” of CMP, Evolving from “Single Head” to “Smart Integration”
The polishing machine is the “main battlefield” of CMP, primarily responsible for rotating the silicon wafer relative to the polishing pad while applying pressure, in conjunction with the slurry to complete the polishing:
- Initially, there were “single-head polishing machines” (polishing one wafer at a time), which later evolved into “multi-head machines” (four modules can polish 80-100 wafers per hour). The structure has also upgraded from traditional rotary types to “track-type” and “linear-type” (for more uniform and efficient polishing);
- International mainstream equipment, such as the IPEC 672-II from the United States and the Toshiba CMS-200 from Japan, can automatically apply pressure, clean, and dry, while at that time, there were no domestically produced CMP devices, completely relying on imports;
- Future trends: Equipment needs to be more integrated (“dry in, dry out” to avoid moisture contamination), support multiple processes (such as polishing + cleaning in one), and adapt to new materials below 0.18μm (such as copper and low-k insulating materials).
2. Polishing Pad: “Cloth + Conveyor Tube,” Hardness Determines Flatness
The polishing pad is not an ordinary “cloth”; it is responsible for delivering the slurry, removing waste, and controlling flatness:
- Hardness is key: hard pads can improve the “uniformity of the entire silicon wafer” (within-wafer uniformity WID), while soft pads can enhance the “uniformity within a single wafer” (die-to-die uniformity WIW). Currently, a “soft-hard pad combination” is commonly used, along with an elastic backing film, to balance both advantages;
- Pain point: Over time, pads can become “glazed” (the surface becomes smooth, making it impossible to retain slurry), requiring regular “reconditioning” (for example, using diamond blades to create a rough surface), otherwise, polishing speed will decrease, which is also part of the consumable cost.
3. Slurry: “Specialized Abrasive Liquid,” Different Materials Require Different “Formulations”
The slurry is the “core ammunition” of CMP, relying on chemical action and mechanical grinding:
- Basic components: ultrafine abrasives (such as SiO₂, Al₂O₃, particle size 1-100nm), oxidizers (to etch the surface), stabilizers (to prevent particle agglomeration), surfactants;
- Targeted formulations: alkaline slurries (pH>10, SiO₂ abrasives) are used for polishing oxides (such as SiO₂), while neutral slurries (pH 5-6, Al₂O₃ abrasives) are used for polishing metals (such as tungsten W). At that time, the research focus was on “copper CMP” (copper is used for interconnects and requires specialized slurries, with countries competing to solve this);
- Goal: To find a balance between “chemical + mechanical” – to polish quickly, achieve a flat surface with few defects, and ensure easy cleaning without corroding the equipment.
4. Key Assistants: Post-Cleaning + Endpoint Detection, A Little Mistake Can Ruin Everything
CMP does not end with polishing; if these two steps are not done well, the silicon wafer will be scrapped:
- Post-cleaning: After polishing, the silicon wafer surface will retain slurry particles and metal impurities (such as Al, Cu), which must be removed to “fewer than 500 particles per square meter.” Common methods include PVA scrubbing (for oxide CMP), dilute HF soaking (to remove metals), and ultrasonic assistance. Now, there are also devices that combine “cleaning + slight etching” for cost reduction and efficiency;
- Endpoint detection: The most troublesome issue – how to know when “enough polishing has been done”? Insufficient polishing leads to unevenness, while excessive polishing can wear through the underlying layer (such as the insulating layer). Early methods relied on “monitoring motor current” (surface changes affect friction resistance), while later methods used laser interferometry (measuring thickness from the back of the wafer) and infrared sensors, but at that time, there was no fully practical solution.
3. The “Three Hurdles” CMP Has Yet to Overcome: Mechanism, Detection, New Materials
Despite CMP becoming mainstream, the document also points out that there are still many unresolved technical challenges that restrict the development of finer processes:
1. Fundamental mechanisms are not fully understood: “More reliance on experience than theory”
Currently, the understanding of CMP remains at a “semi-empirical” stage: for example, how do polishing pressure and rotation speed affect flatness? What are the chemical and physical interactions between the polishing pad, slurry, and silicon wafer? What is the quantitative impact of slurry pH and particle size on polishing effectiveness? These fundamental questions lack comprehensive theoretical models, leading to process parameters relying entirely on “trial and error,” making precise control difficult.
2. Online detection is a “shortcoming”: stable mass production is difficult
Without reliable online endpoint detection, CMP cannot achieve stable mass production – for example, within the same batch of silicon wafers, some may be over-polished while others are under-polished, leading to reduced yield. The detection methods at that time either lacked precision or were too costly to meet the requirements for processes below 0.18μm.
3. New material polishing is a “bottleneck”: copper and low-k dielectrics are new challenges
As devices evolve, new materials have emerged: for example, using copper instead of aluminum for interconnects (lower resistance) and using low-k materials for insulation (to reduce signal interference). However, the CMP processes for these materials were still under research at that time – for instance, copper is soft and prone to “dimpling”; low-k materials are brittle and prone to cracking, requiring redesign of existing slurries and equipment.
4. Domestic “Equipment Gap”: Reliance on Imports, Urgent Demand
The document specifically mentions that at that time, no domestic company could produce CMP equipment, and as the 0.35μm process advanced, the demand for multilayer wiring flattening grew increasingly urgent. “Early development of domestic CMP equipment and processes” had become a pressing task – this also laid the groundwork for subsequent breakthroughs in domestic CMP technology.
4. Conclusion: The Progress of CMP is the Progress of Semiconductors
From IBM’s first application to global proliferation, CMP became an “essential need” for semiconductors in less than ten years. It may seem like a “rough job” such as “polishing,” but it is actually a cross-disciplinary challenge involving chemistry, physics, and fluid mechanics – every breakthrough in CMP technology (such as more precise slurries and smarter detection) can push device processes towards smaller dimensions.
Today, many CMP equipment and consumable companies have emerged domestically, but looking back at the “equipment gap in 2002” recorded in the document, one can better understand the importance of “self-controllability” in the semiconductor industry. In the future, with the arrival of 3nm and 2nm processes, CMP will need to solve even finer planarization and lower defect rates; its story continues.