Recently, I received an FPGA board sent by Gao Yun, as shown in the figure below:
Source: https://wiki.sipeed.com/hardware/zh/tang/tang-primer-20k/primer-20k.html
Main parameters of the FPGA:
| FPGA Model | Parameters |
|---|---|
| GW2A-LV18PG256C8/I7 | Logic Units (LUT4) 20736 |
| Registers (FF) 15552 | |
| Distributed Static RAM S-SRAM (bits) 41472 | |
| Block Static RAM B-SRAM (bits) 828K | |
| Number of Block Static RAM B-SRAM (units) 46 | |
| Multipliers (18×18 Multiplier) 48 | |
| Phase-Locked Loops (PLLs) 4 | |
| Total I/O Banks 8 |
Since the board is from a third party, I will not comment on it. Today, we will briefly discuss the following aspects: EDA, IP, compilation speed, and ecosystem.
EDA
The EDA download from Gao Yun is very straightforward and can be downloaded directly from the following URL:
http://www.gowinsemi.com.cn/faq.aspx
I am using the educational version of the software, which does not require a license, but it does have some limitations.
Opening the interface:
The overall interface is similar to Lattice Diamond, but there is an uncomfortable aspect: files do not have a hierarchical relationship and can only be viewed in hierarchy after synthesis:
This is extremely unfriendly for large or multi-file projects, especially for code inheritance.
After writing the code, the synthesis, layout, and routing interface is very convenient, and can be completed in the interface below.
Pin binding can also be done in two ways: through the interface after synthesis or through physical constraints in a file:
Finally, for layout and routing, you can open the download plugin by clicking on either of the two positions in the image below:
This plugin can be used independently without a license, which is very convenient for small batch production.
However, there is a small bug here: when opening the download plugin, the files shown may not necessarily be the files for your project:
Especially when using a logic analyzer, a new binary file (with a new filename) will be regenerated, and the file location shown above will not update to the new file, requiring you to reselect it. These two points can easily lead to downloading the target file to the FPGA and the generated file not being the same file (I debugged this for a long time…). It would be better if this could not be remembered or if there was a prompt below or an exclamation mark added to the file selection location.
Another advantage of Gao Yun’s FPGA is that it can solidify the startup file without external FLASH, as the FPGA has internal FLASH (similar to Intel CPLD), and it can also use external FLASH for dual backup, which reduces circuit complexity, lowers costs, and increases stability.
IP
Having briefly introduced the use of the EDA software (Gao Yun software), let’s look at the most important part for developers—IP. A powerful IP environment can save developers a lot of development time. Let’s first look at how many IPs are available in the educational version:
The following figure shows the conventional IPs provided by the EDA, which are quite rich, including DSP, common interfaces, CLOCK, Memory, etc. Since I am using the educational version of the EDA, I am not sure what is missing compared to the official version, but there are some IPs that I cannot use, which is normal. Differentiated services are the trend for the future.
Here we focus on the part indicated by the arrow below:
Those engaged in image processing should understand the importance of these IPs. The Video Frame Buffer is similar to AMD-Xilinx’s “VFIFO”, which buffers frames to DDR and reads frame data from DDR for display or processing, greatly reducing the development cycle for developers working with DDR.
Compilation Speed
I won’t elaborate much on this, as the software itself requires little optimization (the internal clock frequency is relatively low), so the speed is quite fast. Once larger capacity and higher frequency FPGAs come out, the speed will definitely decrease, but currently, there is no way to compare.
Ecosystem
I won’t take Gao Yun as an example here, but currently, domestic FPGAs are all the same; the ecosystem is almost non-existent. This is mainly because the focus has been on stabilizing the market in the early stages without promotion, so it is normal that the ecosystem has not been established. With future development, it will definitely improve.
Image Processing Platform
Regarding the code, this document will not go into detail, mainly applying the DDR + FRAME BUFFER two IPs. Detailed project:
https://github.com/sipeed/TangPrimer-20K-example/tree/main/Cam2HDMI
On this basis, you can add your own IP. If everyone is interested, I will explain this project in detail later.
Conclusion
Domestic FPGAs are developing, and currently, they have a significant price advantage. Future development will rely on domestic developers’ support.
Although there are still some bugs, they are bearable. Finally, I hope that domestic FPGAs can continue to develop and improve.
If there are other manufacturers’ domestic FPGAs that need evaluation or use, feel free to leave a message.
END
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